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參數(shù)資料
| 型號： | LTC2450IDC#TRMPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT DELTA SIG 6-DFN |
| 產(chǎn)品培訓(xùn)模塊： | LTC2460 and LTC2450 Delta Sigma ADC Families |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 30 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.05mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 6-DFN-EP（2x2） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
| 產(chǎn)品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 其它名稱： | LTC2450IDC#TRMPBFDKR |
LTC2450
17
2450fb
APPLICATIONS INFORMATION
noise contribution of the external drive circuit would be
Vn = ni √π/2 Fi. Then, the total system noise level can
be estimated as the square root of the sum of (Vn2) and
the square of the LTC2450 noise oor (≈2μV2).
Aliasing
The LTC2450 signal acquisition circuit is a sampled data
system and as such suffers from input signal aliasing. As
can be seen from Figure 19, due to the very high over-
sample ratios the high frequency input signal attenuation
is reasonably good. Nevertheless a continuous time
antialiasing lter connected at the input will preserve
the converter accuracy when the input signal includes
undesirable high frequency components. The antialias-
ing function can be accomplished using the RS and CIN
components shown in Figure 15 sized such that τ = RS
CIN > 450ns.
Figure 18. Input Signal Attenuation vs Frequency
(Low Frequencies)
Figure 19. Input Signal Attenuation vs Frequency
Signal Bandwidth and Noise Equivalent Input
Bandwidth
The LTC2450 includes a sinc1 type digital lter with the
rst notch located at f0 = 60Hz. As such the 3dB input
signal bandwidth is 26.54Hz. The calculated LTC2450
input signal attenuation with frequency at low frequencies
is shown in Figure 18.
The LTC2450 input signal attenuation with frequency over
a wide frequency range is shown in Figure 19.
The converter noise level is about 1.4μVRMS and can be
modeled by a white noise source connected at the input
of a noise free converter.
For a simple system noise analysis the VIN drive circuit can
be modeled as a single pole equivalent circuit character-
ized by a pole location Fi and a noise spectral density ni.
If the converter has an unlimited bandwidth or at least
a bandwidth substantially larger than Fi, then the total
INPUT SIGNAL FREQUENCY (Hz)
0
INPUT
SIGNAL
A
TTENUA
TIOIN
(dB)
–20
–10
0
480
2450 F18
–30
–40
–25
–15
–5
–35
–45
–50
120
60
240
180
360 420
540
300
600
INPUT SIGNAL FREQUENCY (MHz)
0
INPUT
SIGNAL
A
TTENUA
TION
(dB)
–40
0
10.0
12.5
15.0
2450 F19
–60
–80
–20
–100
2.5
5.0
7.5
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