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參數資料
| 型號： | LTC2450IDC-1TRMPBF |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Easy-to-Use, Ultra-Tiny 16-Bit ADC |
| 中文描述： | 易于使用，超微型16位ADC |
| 文件頁數： | 13/20頁 |
| 文件大?。?/td> | 212K |
| 代理商： | LTC2450IDC-1TRMPBF |
LTC2450-1
13
24501fb
APPLICATIONS INFORMATION
2-Wire Operation
The 2-wire operation modes, while reducing the number
of required control signals, should be used only if the
LTC2450-1 low power sleep capability is not required. In
addition the option to abort serial data transfers is no longer
available. Hardwire
CS
to GND for 2-wire operation.
Figure 12 shows a 2-wire operation sequence which uses
an idle-high (CPOL = 1) serial clock signal. The conversion
status can be monitored at the SDO output. Following a
conversion cycle, the ADC enters SLEEP state and the
SDO output transitions from HIGH to LOW. Subsequently
16 clock pulses are applied to the SCK input in order
to serially shift the 16 bit result. Finally, the 17th clock
pulse is applied to the SCK input in order to trigger a new
conversion cycle.
Figure 13 shows a 2-wire operation sequence which uses
an idle-low (CPOL = 0) serial clock signal. The conversion
24501 F12
D
15
D
14
D
13
D
12
D
2
D
1
D
0
SD0
clk
1
clk
2
clk
3
clk
4
clk
15
clk
16
clk
17
SCK
CONVERT
CONVERT
SLEEP
DATA OUTPUT
CS
= LOW
Figure 12. 2-Wire, Idle-High (CPOL = 1) Serial Clock, Operation Example
24501 F13
D
15
D
14
D
13
D
12
D
2
D
1
D
0
SD0
CS
= LOW
clk
1
clk
2
clk
3
clk
14
clk
4
clk
15
clk
16
SCK
CONVERT
CONVERT
DATA OUTPUT
Figure 13. 2-Wire, Idle-Low (CPOL = 0) Serial Clock Operation Example
status cannot be monitored at the SDO output. Following
a conversion cycle, the LTC2450-1 bypasses the SLEEP
state and immediately enters the DATA OUTPUT state. At
this moment the SDO pin outputs the most significant bit
(D15) of the conversion result. The user must use external
timing in order to determine the end of conversion and
result availability. Subsequently 16 clock pulses are applied
to SCK in order to serially shift the 16-bit result. The 16th
clock falling edge triggers a new conversion cycle.
PRESERVING THE CONVERTER ACCURACY
The LTC2450-1 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling,
PCB layout, antialiasing circuits, line and frequency
perturbations. Nevertheless, in order to preserve the
very high accuracy capability of this part, some simple
precautions are desirable.
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