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參數資料
| 型號： | LTC2450CDC-1#TRMPBF |
| 廠商： | Linear Technology |
| 文件頁數： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT DELTA SIG 6-DFN |
| 產品培訓模塊： | LTC2460 and LTC2450 Delta Sigma ADC Families |
| 標準包裝： | 1 |
| 位數： | 16 |
| 采樣率（每秒）： | 30 |
| 數據接口： | 串行，SPI? |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 1.05mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 6-DFN-EP（2x2） |
| 包裝： | 標準包裝 |
| 輸入數目和類型： | 1 個單端，單極 |
| 產品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 其它名稱： | LTC2450CDC-1#TRMPBFDKR |
LTC2450-1
13
24501fc
APPLICATIONS INFORMATION
24501 F12
D15
D14
D13
D12
D2
D1
D0
SD0
clk1
clk2
clk3
clk4
clk15
clk16
clk17
SCK
CONVERT
SLEEP
DATA OUTPUT
CS = LOW
Figure 12. 2-Wire, Idle-High (CPOL = 1) Serial Clock, Operation Example
24501 F13
D15
D14
D13
D12
D2
D1
D0
SD0
CS = LOW
clk1
clk2
clk3
clk14
clk4
clk15
clk16
SCK
CONVERT
DATA OUTPUT
Figure 13. 2-Wire, Idle-Low (CPOL = 0) Serial Clock Operation Example
2-Wire Operation
The 2-wire operation modes, while reducing the number
of required control signals, should be used only if the
LTC2450-1 low power sleep capability is not required. In
addition the option to abort serial data transfers is no longer
available. Hardwire CS to GND for 2-wire operation.
Figure 12 shows a 2-wire operation sequence which uses
an idle-high (CPOL = 1) serial clock signal. The conversion
status can be monitored at the SDO output. Following a
conversion cycle, the ADC enters SLEEP state and the
SDO output transitions from HIGH to LOW. Subsequently
16 clock pulses are applied to the SCK input in order
to serially shift the 16 bit result. Finally, the 17th clock
pulse is applied to the SCK input in order to trigger a new
conversion cycle.
Figure 13 shows a 2-wire operation sequence which uses
an idle-low (CPOL = 0) serial clock signal. The conversion
status cannot be monitored at the SDO output. Following
a conversion cycle, the LTC2450-1 bypasses the SLEEP
state and immediately enters the DATA OUTPUT state. At
this moment the SDO pin outputs the most signicant bit
(D15) of the conversion result. The user must use external
timing in order to determine the end of conversion and
result availability. Subsequently 16 clock pulses are applied
to SCK in order to serially shift the 16-bit result. The 16th
clock falling edge triggers a new conversion cycle.
PRESERVING THE CONVERTER ACCURACY
The LTC2450-1 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling,
PCB layout, antialiasing circuits, line and frequency
perturbations. Nevertheless, in order to preserve the
very high accuracy capability of this part, some simple
precautions are desirable.
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