參數(shù)資料
型號(hào)： LTC2436-1IGN#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 27/28頁(yè)
文件大?。?/td> 0K
描述： IC CONV A/D 16B 2CH DIFF 16SSOP
標(biāo)準(zhǔn)包裝： 100
位數(shù)： 16
采樣率（每秒）： 6.8
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)差分，雙極
LTC2436-1
8
24361f
CONVERTER OPERATION
Converter Operation Cycle
The LTC2436-1 is a low power,
Σ ADC with automatic
alternate channel selection between the two differential
channels and an easy-to-use 3-wire serial interface (see
Figure 1). Channel 0 is selected automatically at power up
and the two channels are selected alternately afterwards
(ping-pong). Its operation is made up of three states. The
converter operating cycle begins with the conversion,
followed by the low power sleep state and ends with the
data output (see Figure 2). The 3-wire interface consists
of serial data output (SDO), serial clock (SCK) and chip
select (CS).
Initially, the LTC2436-1 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
The part remains in the sleep state as long as CS is HIGH.
While in this sleep state, power consumption is reduced by
nearly two orders of magnitude. The conversion result is
held indefinitely in a static shift register while the converter
is in the sleep state.
Once CS is pulled LOW, the device exits the low power
mode and enters the data output state. If CS is pulled HIGH
before the first rising edge of SCK, the device returns to the
low power sleep mode and the conversion result is still
held in the internal static shift register. If CS remains LOW
after the first rising edge of SCK, the device begins
outputting the conversion result. Taking CS high at this
point will terminate the data output state and start a new
conversion. There is no latency in the conversion result.
The data output corresponds to the conversion just per-
formed. This result is shifted out on the serial data out pin
(SDO) under the control of the serial clock (SCK). Data is
updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK (see Figure 3).
The data output state is concluded once 19 bits are read
out of the ADC or when CS is brought HIGH. The device
automatically initiates a new conversion and the cycle
repeats. In order to maintain compatibility with 24-/32-bit
data transfers, it is possible to clock the LTC2436-1 with
additional serial clock pulses. This results in additional
data bits which are always logic HIGH.
Through timing control of the CS and SCK pins, the
LTC2436-1 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require program-
ming configuration registers; moreover, they do not dis-
turb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50Hz and
60Hz plus their harmonics. The filter rejection perfor-
mance is directly related to the accuracy of the converter
system clock. The LTC2436-1 incorporates a highly accu-
rate on-chip oscillator. This eliminates the need for exter-
nal frequency setting components such as crystals or
oscillators. Clocked by the on-chip oscillator, the
LTC2436-1 achieves a minimum of 87dB rejection over
the range 49Hz to 61.2Hz.
Ease of Use
The LTC2436-1 data output has no latency, filter settling
delay or redundant data associated with the conversion
Figure 2. LTC2436-1 State Transition Diagram
APPLICATIO S I FOR ATIO
WU
UU
CONVERT
POWER UP
IN+ = CH0+, IN– = CH0–
SLEEP
DATA OUTPUT
SWITCH CHANNEL
24361 F02
TRUE
FALSE
CS = LOW
AND
SCK
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