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參數資料
| 型號： | LTC2435IGN#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 19/42頁 |
| 文件大小： | 0K |
| 描述： | IC ADC DIFF I/REF 20BIT 16-SSOP |
| 標準包裝： | 100 |
| 位數： | 20 |
| 采樣率（每秒）： | 15 |
| 數據接口： | MICROWIRE?，串行，SPI? |
| 轉換器數目： | 2 |
| 功率耗散（最大）： | 1mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SSOP |
| 包裝： | 管件 |
| 輸入數目和類型： | 1 個差分，雙極 |
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LTC2435/LTC2435-1
26
24351fc
For more information www.linear.com/LTC2435
applicaTions inForMaTion
Driving the Input and Reference
The input and reference pins of the LTC2435/LTC2435-1
convertersaredirectlyconnectedtoanetworkofsampling
capacitors. Depending upon the relation between the dif-
ferentialinputvoltageandthedifferentialreferencevoltage,
these capacitors are switching between these four pins
transferring small amounts of charge in the process. A
simplified equivalent circuit is shown in Figure 14.
For a simple approximation, the source impedance RS
driving an analog input pin (IN+, IN–, REF+ or REF–) can
be considered to form, together with RSW and CEQ (see
Figure 14), a first order passive network with a time
constant
τ = (RS + RSW) CEQ. The converter is able to
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant
τ. The sampling process on
the four input analog pins is quasi-independent so each
time constant should be considered by itself and, under
worst-case circumstances, the errors may add.
When using the internal oscillator (FO = LOW or HIGH),
the LTC2435’s front-end switched-capacitor network is
clocked at 76800Hz corresponding to a 13s sampling
periodandtheLTC2435-1’sfrontendisclockedat69900Hz
corresponding to 14.2s. Thus, for settling errors of less
than 1ppm, the driving source impedance should be
chosen such that
τ ≤ 13s/14 = 920ns (LTC2435) and
τ <14.2s/14 = 1.01s (LTC2435-1). When an external
oscillator of frequency fEOSC is used, the sampling period
is 2/fEOSC and, for a settling error of less than 1ppm, τ ≤
0.14/fEOSC.
Input Current
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 14 shows
the mathematical expressions for the average bias cur-
rents flowing through the IN+ and IN– pins as a result of
Figure 14. LTC2435/LTC2435-1 Equivalent Analog Input Circuit
VREF+
VIN+
VCC
RSW (TYP)
20k
ILEAK
VCC
ILEAK
VCC
RSW (TYP)
20k
CEQ
18pF
(TYP)
RSW (TYP)
20k
ILEAK
IIN+
VIN–
IIN–
IREF+
IREF–
2435 F18
ILEAK
VCC
ILEAK
SWITCHING FREQUENCY
fSW = 76800Hz INTERNAL
OSCILLATOR (LTC2435)
(FO = LOW OR HIGH)
fSW = 69900Hz INTERNAL
OSCILLATOR (LTC2435-1)
(FO = LOW)
fSW = 0.5 fEOSC EXTERNAL OSCILLATOR
VREF–
RSW (TYP)
20k
I IN
V
R
I IN
V
R
I REF
V
R
V
R
I REF
V
R
V
R
where
AVG
IN
INCM
REFCM
EQ
AVG
IN
INCM
REFCM
EQ
AVG
REF
INCM
REFCM
EQ
IN
REF
EQ
AVG
REF
INCM
REFCM
EQ
IN
REF
EQ
+
+
( ) =
+
( ) =
+
(
) =
+
(
) =
+
+
0 5
1 5
0 5
1 5
0 5
2
.
::
V
REF
V
REF
V
IN
V
IN
REF
REFCM
IN
INCM
REQ = 43.2MΩ INTERNAL OSCILLATOR 60Hz NOTCH (FO = LOW) LTC2435
REQ = 52MΩ INTERNAL OSCILLATOR 50Hz NOTCH (FO = HIGH) LTC2435
REQ = 48MΩ INTERNAL OSCILLATOR 50Hz/60Hz NOTCH (FO = LOW) LTC2435-1
REQ = (6.7 1012)/fEOSC EXTERNAL OSCILLATOR
=
=
+
=
=
+
+
+
+
2
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