參數(shù)資料
型號(hào): LTC2435-1CGN#TRPBF
廠商: Linear Technology
文件頁(yè)數(shù): 11/42頁(yè)
文件大?。?/td> 0K
描述: IC ADC DIFF I/REF 20BIT 16-SSOP
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 20
采樣率(每秒): 13.75
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 1mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)差分,雙極
LTC2435/LTC2435-1
19
24351fc
For more information www.linear.com/LTC2435
applicaTions inForMaTion
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift
out the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
The serial clock mode is selected on the falling edge of
CS. To select the external serial clock mode, the serial
clock pin (SCK) must be LOW during each CS falling edge.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may
be pulled LOW in order to monitor the state of the con-
verter. While CS is pulled LOW, EOC is output to the SDO
pin. EOC = 1 while a conversion is in progress and EOC
= 0 if the conversion is over. With CS HIGH, the device
automatically enters the sleep state once the conversion
is complete.
When CS is low, the device enters the data output mode.
The result is held in the internal static shift register until
the first SCK rising edge is seen while CS is LOW. Data
is shifted out the SDO pin on each falling edge of SCK.
This enables external circuitry to latch the output on the
rising edge of SCK. EOC can be latched on the first rising
edge of SCK and the last bit of the conversion result can
be latched on the 24th rising edge of SCK. On the 24th
falling edge of SCK, the device begins a new conversion.
SDO goes HIGH (EOC = 1) indicating a conversion is in
progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time
in order to monitor the conversion status.
Figure 8. External Serial Clock, Single Cycle Operation
EOC
BIT 23
SDO
SCK
(EXTERNAL)
CS
TEST EOC
LSB
MSB
SIG
BIT 0
BIT 5
BIT 19
BIT 18
BIT 20
BIT 21
BIT 22
SLEEP
DATA OUTPUT
CONVERSION
2435 F08
CONVERSION
= 50Hz REJECTION (LTC2435)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2435)
= 50Hz/60Hz REJECTION (LTC2435-1)
Hi-Z
VCC
TEST EOC
VCC
FO
REF+
REF
SCK
IN+
IN
SDO
GND
CS
2
14
3
4
13
5
6
12
1, 7, 8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1
F
2.7V TO 5.5V
LTC2435/
LTC2435-1
3-WIRE
SPI INTERFACE
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