For relatively small values of input capacitance (CIN
參數(shù)資料
型號: LTC2413CGN
廠商: Linear Technology
文件頁數(shù): 19/44頁
文件大?。?/td> 0K
描述: IC A/D CONV 24BIT MICRPWR 16SSOP
標準包裝: 100
位數(shù): 24
采樣率(每秒): 6.8
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉換器數(shù)目: 2
功率耗散(最大): 1mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 16-SSOP
包裝: 管件
輸入數(shù)目和類型: 1 個差分,雙極
LTC2413
26
sn2413 2413fs
APPLICATIO S I FOR ATIO
WU
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For relatively small values of input capacitance (CIN <
0.01
F), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
source impedance result in only small errors. Such values
for CIN will deteriorate the converter offset and gain
performance without significant benefits of signal filtering
and the user is advised to avoid them. Nevertheless, when
small values of CIN are unavoidably present as parasitics
of input multiplexers, wires, connectors or sensors, the
LTC2413 can maintain its exceptional accuracy while
operating with relative large values of source resistance as
shown in Figures 18 and 19. These measured results may
be slightly different from the first order approximation
suggested earlier because they include the effect of the
actual second order input network together with the non-
linear settling process of the input amplifiers. For small CIN
values, the settling on IN+ and INoccurs almost indepen-
dently and there is little benefit in trying to match the
source impedance for the two pins.
Larger values of input capacitors (CIN > 0.01F) may be
required in certain configurations for antialiasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When internal oscillator is used (FO= LOW), the typical
differential input resistance is 2M
which will generate a
gain error of approximately 0.25ppm for each ohm of
source resistance driving IN+ or IN. When FO is driven by
an external oscillator with a frequency fEOSC (external
conversion clock operation), the typical differential input
resistance is 0.28 1012/fEOSC and each ohm of
source resistance driving IN+ or INwill result in
1.78 10–6 fEOSCppm gain error. The effect of the source
resistance on the two input pins is additive with respect to
this gain error. The typical +FS and –FS errors as a function
of the sum of the source resistance seen by IN+ and INfor
large values of CIN are shown in Figures 20 and 21.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
IN+ and INand with the difference between the input and
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the
converter average input current will not degrade the INL
performance, indirect distortion may result from the modu-
lation of the offset error by the common mode component
of the input signal. Thus, when using large CIN capacitor
values, it is advisable to carefully match the source imped-
ance seen by the IN+ and INpins. When internal oscillator
is used (FO = LOW), every 1 mismatch in source imped-
ance transforms a full-scale common mode input signal
into a differential mode input signal of 0.25ppm. When FO
is driven by an external oscillator with a frequency fEOSC,
every 1
mismatch in source impedance transforms a
full-scale common mode input signal into a differential
mode input signal of 1.78 10–6 fEOSCppm. Figure 22
shows the typical offset error due to input common mode
voltage for various values of source resistance imbalance
between the IN+ and INpins when large CIN values are
used.
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/
°C) are
used for the external source impedance seen by IN+ and
IN, the expected drift of the dynamic current, offset and
gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications a one-time cali-
bration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (
±10nA max), results
in a small offset shift. A 100
source resistance will create
a 0.1
V typical and 1V maximum offset voltage.
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