參數(shù)資料
型號： LTC2412CGN#TR
廠商： Linear Technology
文件頁數(shù)： 20/36頁
文件大?。?/td> 0K
描述： IC CONV A/D 24B 2CH DIFF 16-SSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 24
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個差分，雙極
配用： DC746A-ND - BOARD DELTA SIGMA ADC LTC2412
LTC2412
27
2412f
APPLICATIO S I FOR ATIO
WU
U
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
When FO = LOW (internal oscillator and 60Hz notch), every
100
of source resistance driving REF+ or REF– translates
into about 1.34ppm additional INL error. When FO = HIGH
(internal oscillator and 50Hz notch), every 100
of source
resistance driving REF+ or REF– translates into about
1.1ppm additional INL error. When FO is driven by an
external oscillator with a frequency fEOSC, every 100 of
source resistance driving REF+ or REF– translates into
about 8.73 10–6 fEOSCppm additional INL error.
Figure 22 shows the typical INL error due to the source
resistance driving the REF+ or REF– pins when large CREF
values are used. The effect of the source resistance on the
two reference pins is additive with respect to this INL error.
In general, matching of source impedance for the REF+
and REF– pins does not help the gain or the INL error. The
user is thus advised to minimize the combined source
impedance driving the REF+ and REF– pins rather than to
try to match it.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
0.5%. Such a specification can also be easily achieved by
an external clock. When relatively stable resistors
Figure 18. +FS Error vs RSOURCE at REF+ or REF– (Small CIN)
Figure 19. –FS Error vs RSOURCE at REF
+ or REF– (Small CIN)
Figure 20. +FS Error vs RSOURCE at REF+ and REF– (Large CREF)
Figure 21. –FS Error vs RSOURCE at REF+ and REF– (Large CREF)
RSOURCE ()
1
10
100
1k
10k
100k
+FS
ERROR
(ppm
OF
V
REF
)
2412 F18
0
–10
–20
–30
–40
–50
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = 5V
IN – = 2.5V
FO = GND
TA = 25°C
CREF = 0.01F
CREF = 0.001F
CREF = 100pF
CREF = 0pF
RSOURCE ()
1
10
100
1k
10k
100k
–
FS
ERROR
(ppm
OF
V
REF
)
2412 F19
50
40
30
20
10
0
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = GND
IN – = 2.5V
FO = GND
TA = 25°C
CREF = 0.01F
CREF = 0.001F
CREF = 100pF
CREF = 0pF
RSOURCE ()
0 100 200 300 400 500 600 700 800 900 1000
+
FS
ERROR
(ppm
OF
V
REF
)
2412 F20
0
–90
–180
–270
–360
–450
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
CREF = 0.01F
CREF = 0.1F
CREF = 1F, 10F
RSOURCE ()
0 100 200 300 400 500 600 700 800 900 1000
–
FS
ERROR
(ppm
OF
V
REF
)
2412 F21
450
360
270
180
90
0
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
CREF = 0.01F
CREF = 0.1F
CREF = 1F, 10F
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