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參數(shù)資料
| 型號： | LTC2412CGN#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 18/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 2CH DIFF-IN 24BIT 16SSOP |
| 標準包裝： | 100 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 1347 (CN2011-ZH PDF) |
| 配用： | DC746A-ND - BOARD DELTA SIGMA ADC LTC2412 |
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LTC2412
25
2412f
APPLICATIO S I FOR ATIO
WU
U
of input multiplexers, wires, connectors or sensors, the
LTC2412 can maintain its exceptional accuracy while
operating with relative large values of source resistance as
shown in Figures 13 and 14. These measured results may
be slightly different from the first order approximation
suggested earlier because they include the effect of the
actual second order input network together with the non-
linear settling process of the input amplifiers. For small CIN
values, the settling on IN+ and IN– occurs almost indepen-
dently and there is little benefit in trying to match the
source impedance for the two pins.
Larger values of input capacitors (CIN > 0.01F) may be
required in certain configurations for antialiasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When FO = LOW (internal oscillator and 60Hz notch), the
typical differential input resistance is 1.8M
which will
generate a gain error of approximately 0.28ppm at full-
scale for each ohm of source resistance driving IN+ or IN.
When FO = HIGH (internal oscillator and 50Hz notch), the
typical differential input resistance is 2.16M
which will
generate a gain error of approximately 0.23ppm at full-
scale for each ohm of source resistance driving IN+ or IN.
When FO is driven by an external oscillator with a fre-
quency fEOSC (external conversion clock operation), the
typical differential input resistance is 0.28 1012/fEOSC
and each ohm of source resistance driving IN+ or IN– will
result in 1.78 10–6 fEOSCppm gain error at full-scale. The
effect of the source resistance on the two input pins is
additive with respect to this gain error. The typical +FS and
–FS errors as a function of the sum of the source resis-
tance seen by IN+ and IN– for large values of CIN are shown
in Figures 15 and 16.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
IN+ and IN– and with the difference between the input and
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the con-
verter average input current will not degrade the INL
performance, indirect distortion may result from the modu-
lation of the offset error by the common mode component
of the input signal. Thus, when using large CIN capacitor
values, it is advisable to carefully match the source imped-
ance seen by the IN+ and IN– pins. When FO = LOW
(internal oscillator and 60Hz notch), every 1
mismatch
in source impedance transforms a full-scale common
mode input signal into a differential mode input signal of
0.28ppm. When FO = HIGH (internal oscillator and 50Hz
notch), every 1
mismatch in source impedance trans-
forms a full-scale common mode input signal into a differ-
ential mode input signal of 0.23ppm. When FO is driven by
an external oscillator with a frequency fEOSC, every 1
mismatch in source impedance transforms a full-scale
common mode input signal into a differential mode input
signal of 1.78 10–6 fEOSCppm. Figure 17 shows the
typical offset error due to input common mode voltage for
Figure 15. +FS Error vs RSOURCE at IN+ or IN– (Large CIN)
Figure 16. –FS Error vs RSOURCE at IN
+ or IN– (Large CIN)
RSOURCE ()
0 100 200 300 400 500 600 700 800 900 1000
+FS
ERROR
(ppm
OF
V
REF
)
2412 F15
300
240
180
120
60
0
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = 3.75V
IN– = 1.25V
FO = GND
TA = 25°C
CIN = 0.01F
CIN = 0.1F
CIN = 1F, 10F
RSOURCE ()
0 100 200 300 400 500 600 700 800 900 1000
–
FS
ERROR
(ppm
OF
V
REF
)
2412 F16
0
–60
–120
–180
–240
–300
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = 1.25V
IN– = 3.75V
FO = GND
TA = 25°C
CIN = 0.01F
CIN = 0.1F
CIN = 1F, 10F
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