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參數(shù)資料
| 型號： | LTC2411IMS#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 16/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 24BIT MICRPWR 10MSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 1mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
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LTC2411/LTC2411-1
23
a 13
s (14.2s) sampling period. Thus, for settling errors
of less than 1ppm, the driving source impedance should
be chosen such that
τ ≤ 13s/14 = 920ns (1.02s). When
an external oscillator of frequency fEOSC is used, the
sampling period is 2/fEOSC and, for a settling error of less
than 1ppm,
τ ≤ 0.14/fEOSC.
Input Current
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 11 shows the
mathematical expressions for the average bias currents
flowing through the IN+ and IN– pins as a result of the
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 12. The CPAR capacitor
includes the LTC2411/LTC2411-1 pin capacitance (5pF
typical) plus the capacitance of the test fixture used to
obtain the results shown in Figures 13 and 14. A careful
implementation can bring the total input capacitance (CIN
+ CPAR) closer to 5pF thus achieving better performance
than the one predicted by Figures 13 and 14. The effect of
the input dynamic current is almost the same for the
LTC2411 and the LTC2411-1 and measurements of the
LTC2411 with FO = GND are plotted out as a typical case.
For simplicity, two distinct situations can be considered.
For relatively small values of input capacitance (CIN <
0.01
F), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
source impedance result in only small errors. Such values
for CIN will deteriorate the converter offset and gain
performance without significant benefits of signal filter-
ing and the user is advised to avoid them. Nevertheless,
when small values of CIN are unavoidably present as
parasitics of input multiplexers, wires, connectors or
sensors, the LTC2411/LTC2411-1 can maintain their ex-
ceptional accuracy while operating with relative large
values of source resistance as shown in Figures 13 and
14. These measured results may be slightly different from
the first order approximation suggested earlier because
they include the effect of the actual second order input
network together with the nonlinear settling process of
the input amplifiers. For small CIN values, the settling on
IN+ and IN– occurs almost independently and there is little
benefit in trying to match the source impedance for the
two pins.
APPLICATIO S I FOR ATIO
WU
UU
CIN
2411 F12
VINCM + 0.5VIN
RSOURCE
CPAR
20pF
CIN
VINCM – 0.5VIN
RSOURCE
CPAR
20pF
IN+
IN –
LTC2411/
LTC2411-1
RSOURCE ()
1
10
100
1k
10k
100k
+FS
ERROR
(ppm
OF
V
REF
)
2411 F13
50
40
30
20
10
0
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 5V
IN– = 2.5V
FO = GND
TA = 25°C
CIN = 0.01F
CIN = 0pF
CIN = 0.001F
CIN = 100pF
RSOURCE ()
1
10
100
1k
10k
100k
–
FS
ERROR
(ppm
OF
V
REF
)
2411 F14
0
–10
–20
–30
–40
–50
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = GND
IN– = 2.5V
FO = GND
TA = 25°C
CIN = 0pF
CIN = 0.001F
CIN = 100pF
CIN = 0.01F
Figure 12. An RC Network at IN+ and IN–
Figure 13. +FS Error vs RSOURCE at IN+ or IN– (Small CIN)
Figure 14. –FS Error vs RSOURCE at IN
+ or IN– (Small CIN)
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