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參數資料
| 型號： | LTC2391IUK-16#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 6/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16B SER/PAR 250KSPS 48QFN |
| 標準包裝： | 52 |
| 位數： | 16 |
| 采樣率（每秒）： | 250k |
| 數據接口： | 串行，并聯 |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 125mW |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 48-QFN-EP（7x7） |
| 包裝： | 管件 |
| 輸入數目和類型： | 1 個差分，雙極 |
| 配用： | DC1500A-C-ND - BOARD SAR ADC LTC2391-16 |
LTC2391-16
14
239116fa
APPLICATIONS INFORMATION
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the rst ve harmonics and DC. Figure 5 shows
that the LTC2391-16 achieves a typical SNR of 94dB at a
250kHz sampling rate with a 20kHz input.
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
THD
= 20log
V2
2
+ V32 + V42...VN2
V1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the second
through Nth harmonics.
POWER CONSIDERATIONS
The LTC2391-16 provides three sets of power supply
pins: the analog 5V power supply (AVP), the digital 5V
power supply (DVP) and the digital input/output interface
power supply (OVP). The exible OVP supply allows the
LTC2391-16tocommunicatewithanydigitallogicoperating
between 1.8V and 5V, including 2.5V and 3.3V systems.
Power Supply Sequencing
The LTC2391-16 does not have any specic power supply
sequencing requirements. Care should be taken to observe
the maximum voltage relationships described in the Ab-
solute Maximum Ratings section. The LTC2391-16 has a
power-on reset (POR) circuit. With the POR, the result of
the rst conversion is valid after power has been applied
to the ADC. The LTC2391-16 will reset itself if the power
supply voltage drops below 2.5V. Once the supply voltage
is brought back to its nominal value, the POR will reinitial-
ize the ADC and it will be ready to start a new conversion.
Nap Mode
The LTC2391-16 can be put into the nap mode after a
conversion has been completed to reduce the power
consumption between conversions. In this mode some
of the circuitry on the device is turned off. Nap mode is
enabled by keeping CNVST low between conversions. When
the next conversion is requested, bring CNVST high and
hold for at least 250ns, then start the next conversion by
bringing CNVST low. See Figure 6.
Power Shutdown Mode
When PD is tied high, the LTC2391-16 enters power
shutdown and subsequent requests for conversion are
ignored. Before entering power shutdown, the digital
output data needs to be read. However, if a request for
power shutdown (PD = high) occurs during a conversion,
the conversion will nish and then the device will power
down. The data from that conversion can be read after PD
Figure 6. Nap Mode Timing for the LTC2391-16
CNVST
BUSY
NAP
tCONV
tACQ
NAP MODE
239116 F06
t5
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