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參數(shù)資料
| 型號： | LTC2364IDE-18#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT 250K 1CH 16DFN |
| 產(chǎn)品培訓模塊： | LTC2369- 18-/16-bit Pseudo-Differential SAR ADC Family Overview |
| 標準包裝： | 91 |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 4.25mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 16-DFN（4x3） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個偽差分，單極 |
| 配用： | DC1813A-H-ND - BOARD SAR ADC LTC2364-18 |
LTC2364-18
8
236418f
CHAIN (Pin 1): Chain Mode Selector Pin. When low, the
LTC2364-18 operates in normal mode and the RDL/SDI
input pin functions to enable or disable SDO. When high,
the LTC2364-18 operates in chain mode and the RDL/SDI
pin functions as SDI, the daisy-chain serial data input.
Logic levels are determined by OVDD.
VDD (Pin 2): 2.5V Power Supply. The range of VDD is
2.375V to 2.625V. Bypass VDDtoGNDwitha10Fceramic
capacitor.
GND (Pins 3, 6, 10 and 16): Ground.
IN+ (Pin 4): Analog Input. IN+ operates differential with
respect to IN– with an IN+-IN– range of 0V to VREF.
IN– (Pin 5): Analog Ground Sense. IN– has an input range
of ±100mV with respect to GND and must be tied to the
ground plane or a remote ground sense.
REF(Pins7,8):ReferenceInputs.TherangeofREFis2.5V
to 5.1V. This pin is referred to the GND pin and should be
decoupled closely to the pin with a 47F ceramic capacitor
(X5R, 0805 size).
CNV (Pin 9): Convert Input. A rising edge on this input
powers up the part and initiates a new conversion. Logic
levels are determined by OVDD.
BUSY (Pin 11): BUSY Indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by OVDD.
RDL/SDI (Pin 12): When CHAIN is low, the part is in nor-
mal mode and the pin is treated as a bus enabling input.
When CHAIN is high, the part is in chain mode and the
pin is treated as a serial data input pin where data from
another ADC in the daisy chain is input. Logic levels are
determined by OVDD.
SCK(Pin13):SerialDataClockInput.WhenSDOisenabled,
the conversion result or daisy-chain data from another
ADC is shifted out on the rising edges of this clock MSB
first. Logic levels are determined by OVDD.
SDO (Pin 14): Serial Data Output. The conversion result
or daisy-chain data is output on this pin on each rising
edge of SCK MSB first. The output data is in straight binary
format. Logic levels are determined by OVDD.
OVDD (Pin 15): I/O Interface Digital Power. The range of
OVDD is 1.71V to 5.25V. This supply is nominally set to
the same supply as the host interface (1.8V, 2.5V, 3.3V,
or 5V). Bypass OVDD to GND with a 0.1F capacitor.
GND (Exposed Pad Pin 17, DFN Package Only): Ground.
Exposedpadmustbesoldereddirectlytothegroundplane.
PIN FUNCTIONS
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| LTC2364IMS-16#PBF | 制造商:Linear Technology 功能描述:ADC 16BIT 250KSPS SPI DFN-16 |
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| LTC2364IMS-18#PBF | 功能描述:IC ADC 18BIT 250K 1CH 16MSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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