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參數(shù)資料
| 型號： | LTC2299IUP#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DUAL 14BIT 80MSPS 64QFN |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 516mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN（9x9） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，雙極; 2 個差分, 雙極 |
LTC2299
5
2299fa
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fs
Sampling Frequency
(Note 9)
●
1
80
MHz
tL
CLK Low Time
Duty Cycle Stabilizer Off
●
5.9
6.25
500
ns
Duty Cycle Stabilizer On (Note 9)
●
5
6.25
500
ns
tH
CLK High Time
Duty Cycle Stabilizer Off
●
5.9
6.25
500
ns
Duty Cycle Stabilizer On (Note 9)
●
5
6.25
500
ns
tAP
Sample-and-Hold Aperture Delay
0
ns
tD
CLK to DATA Delay
CL = 5pF (Note 7)
●
1.4
2.7
5.4
ns
tMD
MUX to DATA Delay
CL = 5pF (Note 7)
●
1.4
2.7
5.4
ns
Data Access Time After OE
↓
CL = 5pF (Note 7)
●
4.3
10
ns
BUS Relinquish Time
(Note 7)
●
3.3
8.5
ns
Pipeline Latency
5
Cycles
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
Analog Supply Voltage
(Note 9)
●
2.7
3
3.4
V
OVDD
Output Supply Voltage
(Note 9)
●
0.5
3
3.6
V
IVDD
Supply Current
Both ADCs at fS(MAX)
●
148
172
mA
PDISS
Power Dissipation
Both ADCs at fS(MAX)
●
444
516
mW
PSHDN
Shutdown Power (Each Channel)
SHDN = H, OE = H, No CLK
2
mW
PNAP
Nap Mode Power (Each Channel)
SHDN = H, OE = L, No CLK
15
mW
POWER REQUIRE E TS
W
U
The
● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
TI I G CHARACTERISTICS
U
W
The
● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 80MHz, input range = 2VP-P with differential
drive, unless otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and
11 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 80MHz, input range = 1VP-P with differential
drive. The supply current and power dissipation are the sum total for both
channels with both channels active.
Note 9: Recommended operating conditions.
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