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參數資料
| 型號： | LTC2289CUP#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 4/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL 10BIT 80MSPS 64QFN |
| 標準包裝： | 40 |
| 位數： | 10 |
| 采樣率（每秒）： | 80M |
| 數據接口： | 并聯 |
| 轉換器數目： | 2 |
| 功率耗散（最大）： | 495mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 64-QFN（9x9） |
| 包裝： | 管件 |
| 輸入數目和類型： | 2 個單端，雙極; 2 個差分, 雙極 |
| 產品目錄頁面： | 1349 (CN2011-ZH PDF) |
LTC2289
12
2289fa
applications, the analog inputs can be driven single-ended
with slightly worse harmonic distortion. The CLK input is
single-ended. The LTC2289 has two phases of operation,
determined by the state of the CLK input pin.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H during
this high phase of CLK. When CLK goes back low, the first
stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back
to acquiring the analog input. When CLK goes back high,
the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
APPLICATIO S I FOR ATIO
WU
U
third, fourth and fifth stages, resulting in a fifth stage
residue that is sent to the sixth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2289
CMOS differential sample-and-hold. The analog inputs are
connected to the sampling capacitors (CSAMPLE) through
NMOS transistors. The capacitors shown attached to each
input (CPARASITIC) are the summation of all other capaci-
tance associated with each input.
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage.
When CLK transitions from low to high, the sampled input
voltage is held on the sampling capacitors. During the hold
phase when CLK is high, the sampling capacitors are
disconnected from the input and the held voltage is passed
to the ADC core for processing. As CLK transitions from
Figure 2. Equivalent Input Circuit
VDD
15
15
CPARASITIC
1pF
CPARASITIC
1pF
CSAMPLE
4pF
CSAMPLE
4pF
LTC2289
AIN
+
AIN
–
CLK
2289 F02
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LTC2289IUP | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 10-Bit, 80Msps Low Noise 3V ADC |
| LTC2289IUP#PBF | 功能描述:IC ADC DUAL 10BIT 80MSPS 64QFN RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
| LTC2289IUP#TRPBF | 功能描述:IC ADC DUAL 10BIT 80MSPS 64QFN RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
| LTC2289UP | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 10-Bit, 80Msps Low Noise 3V ADC |
| LTC2290 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 12-Bit, 10Msps Low Power 3V ADC |
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