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LTC2288/LTC2287/LTC2286
12
228876f
MUX (Pin 21):
Digital Output Multiplexer Control. If MUX
is High, Channel A comes out on DA0-DA13, OFA; Channel B
comes out on DB0-DB13, OFB. If MUX is Low, the output
busses are swapped and Channel A comes out on DB0-
DB13, OFB; Channel B comes out on DA0-DA13, OFA. To
multiplex both channels onto a single output bus, connect
MUX, CLKA and CLKB together.
SHDNB (Pin 22):
Channel B Shutdown Mode Selection
Pin. Connecting SHDNB to GND and OEB to GND results
in normal operation with the outputs enabled. Connecting
SHDNB to GND and OEB to V
DD
results in normal opera-
tion with the outputs at high impedance. Connecting
SHDNB to V
DD
and OEB to GND results in nap mode with
the outputs at high impedance. Connecting SHDNB to V
DD
and OEB to V
DD
results in sleep mode with the outputs at
high impedance.
OEB (Pin 23):
Channel B Output Enable Pin. Refer to
SHDNB pin function.
NC (Pins 24 to 27, 41 to 44):
Do Not Connect These Pins.
DB0 – DB9 (Pins 28 to 30, 33 to 39):
Channel B Digital
Outputs. DB9 is the MSB.
OGND (Pins 31, 50):
Output Driver Ground.
OV
DD
(Pins 32, 49):
Positive Supply for the Output Driv-
ers. Bypass to ground with 0.1
μ
F ceramic chip capacitor.
OFB (Pin 40):
Channel B Overflow/Underflow Output.
High when an overflow or underflow has occurred.
DA0 – DA9 (Pins 45 to 48, 51 to 56):
Channel A Digital
Outputs. DA9 is the MSB.
OFA (Pin 57):
Channel A Overflow/Underflow Output.
High when an overflow or underflow has occurred.
OEA (Pin 58):
Channel A Output Enable Pin. Refer to
SHDNA pin function.
SHDNA (Pin 59):
Channel A Shutdown Mode Selection
Pin. Connecting SHDNA to GND and OEA to GND results
in normal operation with the outputs enabled. Connecting
SHDNA to GND and OEA to V
DD
results in normal opera-
tion with the outputs at high impedance. Connecting
SHDNA to V
DD
and OEA to GND results in nap mode with
the outputs at high impedance. Connecting SHDNA to V
DD
and OEA to V
DD
results in sleep mode with the outputs at
high impedance.
MODE (Pin 60):
Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Note that MODE controls both
channels. Connecting MODE to GND selects straight bi-
nary output format and turns the clock duty cycle stabilizer
off. 1/3 V
DD
selects straight binary output format and turns
the clock duty cycle stabilizer on. 2/3 V
DD
selects 2’s
complement output format and turns the clock duty cycle
stabilizer on. V
DD
selects 2’s complement output format
and turns the clock duty cycle stabilizer off.
V
CMA
(Pin 61):
Channel A 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2
μ
F ceramic chip
capacitor. Do not connect to V
CMB
.
SENSEA (Pin 62):
Channel A Reference Programming Pin.
Connecting SENSEA to V
CMA
selects the internal reference
and a
±
0.5V input range. V
DD
selects the internal reference
and a
±
1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEA selects an input
range of
±
V
SENSEA
.
±
1V is the largest valid input range.
GND (Exposed Pad) (Pin 65):
ADC Power Ground. The
Exposed Pad on the bottom of the package needs to be
soldered to ground.
PIU