參數(shù)資料
型號(hào): LTC2288IUP
廠商: LINEAR TECHNOLOGY CORP
元件分類(lèi): ADC
英文描述: Dual 10-Bit, 65/40/25Msps Low Noise 3V ADCs
中文描述: DUAL 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
封裝: 9 X 9 MM, PLASTIC, MO-220-WNJR-5, QFN-64
文件頁(yè)數(shù): 5/28頁(yè)
文件大?。?/td> 886K
代理商: LTC2288IUP
LTC2288/LTC2287/LTC2286
5
228876f
POWER REQUIREW
range, otherwise specifications are at T
A
= 25
°
C. (Note 8)
U
The
denotes the specifications which apply over the full operating temperature
TIW
range, otherwise specifications are at T
A
= 25
°
C. (Note 4)
The
denotes the specifications which apply over the full operating temperature
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3:
When these pin voltages are taken below GND or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V
DD
without latchup.
Note 4:
V
DD
= 3V, f
SAMPLE
= 65MHz (LTC2288), 40MHz (LTC2287), or
25MHz (LTC2286), input range = 2V
P-P
with differential drive, unless
otherwise noted.
Note 5:
Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6:
Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 and 11 1111 1111.
Note 7:
Guaranteed by design, not subject to test.
Note 8:
V
DD
= 3V, f
SAMPLE
= 65MHz (LTC2288), 40MHz (LTC2287), or
25MHz (LTC2286), input range = 1V
P-P
with differential drive. The supply
current and power dissipation are the sum total for both channels with
both channels active.
Note 9:
Recommended operating conditions.
LTC2288
TYP
3
LTC2287
TYP
3
LTC2286
TYP
3
SYMBOL
V
DD
PARAMETER
Analog Supply
Voltage
Output Supply
Voltage
Supply Current
Power Dissipation
Shutdown Power
(Each Channel)
Nap Mode Power
(Each Channel)
CONDITIONS
(Note 9)
MIN
2.7
MAX
3.4
MIN
2.7
MAX
3.4
MIN
2.7
MAX
3.4
UNITS
V
OV
DD
(Note 9)
0.5
3
3.6
0.5
3
3.6
0.5
3
3.6
V
IV
DD
P
DISS
P
SHDN
Both ADCs at f
S(MAX)
Both ADCs at f
S(MAX)
SHDN = H,
OE = H, No CLK
SHDN = H,
OE = L, No CLK
133
400
2
150
450
78
235
2
95
285
50
150
2
60
180
mA
mW
mW
P
NAP
15
15
15
mW
LTC2288
TYP
LTC2287
TYP
LTC2286
TYP
SYMBOL
f
s
t
L
PARAMETER
Sampling Frequency (Note 9)
CLK Low Time
CONDITIONS
MIN
1
7.3
5
MAX
65
500
500
MIN
1
11.8
5
MAX
40
500
500
MIN
1
18.9
5
MAX
25
500
500
UNITS
MHz
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
7.7
7.7
12.5
12.5
20
20
ns
ns
t
H
CLK High Time
7.3
5
7.7
7.7
500
500
11.8
5
12.5
12.5
500
500
18.9
5
20
20
500
500
ns
ns
t
AP
Sample-and-Hold
Aperture Delay
CLK to DATA Delay
MUX to DATA Delay C
L
= 5pF (Note 7)
Data Access Time
After OE
BUS Relinquish Time (Note 7)
0
0
0
ns
t
D
t
MD
C
L
= 5pF (Note 7)
1.4
1.4
2.7
2.7
4.3
5.4
5.4
10
1.4
1.4
2.7
2.7
4.3
5.4
5.4
10
1.4
1.4
2.7
2.7
4.3
5.4
5.4
10
ns
ns
ns
C
L
= 5pF (Note 7)
3.3
6
8.5
3.3
6
8.5
3.3
6
8.5
ns
Pipeline
Latency
Cycles
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