參數(shù)資料
型號： LTC2280CUP#TRPBF
廠商： Linear Technology
文件頁數(shù)： 24/24頁
文件大?。?/td> 0K
描述： IC ADC DUAL 10BIT 105MSPS 64-QFN
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 10
采樣率（每秒）： 105M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 630mW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 64-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-QFN（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個單端，雙極; 2 個差分, 雙極
LTC2280
9
2280fa
SHIFT REGISTER
AND CORRECTION
DIFF
REF
AMP
REF
BUF
2.2
F
1
F1F
0.1
F
INTERNAL CLOCK SIGNALS
REFH
REFL
CLOCK/DUTY
CYCLE
CONTROL
RANGE
SELECT
1.5V
REFERENCE
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
SIXTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
REFH
REFL
CLK
OE
MODE
OGND
OVDD
2280 F01
INPUT
S/H
SENSE
VCM
AIN
–
AIN
+
2.2
F
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
CONTROL
LOGIC
SHDN
OF
D9
D0
SHDNA (Pin 59): Channel A Shutdown Mode Selection
Pin. Connecting SHDNA to GND and OEA to GND results
in normal operation with the outputs enabled. Connecting
SHDNA to GND and OEA to VDD results in normal opera-
tion with the outputs at high impedance. Connecting
SHDNA to VDD and OEA to GND results in nap mode with
the outputs at high impedance. Connecting SHDNA to VDD
and OEA to VDD results in sleep mode with the outputs at
high impedance.
MODE (Pin 60): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Note that MODE controls both
channels. Connecting MODE to GND selects offset binary
output format and turns the clock duty cycle stabilizer off.
1/3 VDD selects offset binary output format and turns the
clock duty cycle stabilizer on. 2/3 VDD selects 2’s comple-
ment output format and turns the clock duty cycle
UU
U
PI FU CTIO S
stabilizer on. VDD selects 2’s complement output format
and turns the clock duty cycle stabilizer off.
VCMA (Pin 61): Channel A 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2
F ceramic chip
capacitor. Do not connect to VCMB.
SENSEA (Pin 62): Channel A Reference Programming Pin.
Connecting SENSEA to VCMA selects the internal reference
and a
±0.5V input range. VDD selects the internal reference
and a
±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEA selects an input
range of
±VSENSEA. ±1V is the largest valid input range.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
Exposed Pad on the bottom of the package needs to be
soldered to ground.
FUNCTIONAL BLOCK DIAGRA
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W
Figure 1. Functional Block Diagram (Only One Channel is Shown)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LTC2280IUP 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 10-Bit, 105Msps Low Noise 3V ADC
LTC2280IUP#PBF 功能描述:IC ADC DUAL 10BIT 105MSPS 64-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6
LTC2280IUP#TRPBF 功能描述:IC ADC DUAL 10BIT 105MSPS 64-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極
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