參數(shù)資料
型號： LTC2268IUJ-14#PBF
廠商： Linear Technology
文件頁數(shù)： 28/32頁
文件大小： 0K
描述： IC ADC 14BIT SER 125MSPS 40-QFN
標(biāo)準(zhǔn)包裝： 61
位數(shù)： 14
采樣率（每秒）： 125M
數(shù)據(jù)接口： Serial LVDS
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 364mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-QFN（6x6）
包裝： 管件
輸入數(shù)目和類型： 2 Differential; 2 Single-Ended
配用： DC1371A-ND - BOARD USB DATA ACQUISITION HS
LTC2268-14/
LTC2267-14/LTC2266-14
5
22687614fa
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
VIH
High Level Input Voltage
VDD =1.8V
l
1.3
V
VIL
Low Level Input Voltage
VDD =1.8V
l
0.6
V
IIN
Input Current
VIN = 0V to 3.6V
l
–10
10
A
CIN
Input Capacitance
3
pF
SDO OUTPUT (Serial Programming Mode. Open Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used)
ROL
Logic Low Output Resistance to GND
VDD =1.8V, SDO = 0V
200
Ω
IOH
Logic High Output Leakage Current
SDO = 0V to 3.6V
l
–10
10
A
COUT
Output Capacitance
3
pF
DIGITAL DATA OUTPUTS
VOD
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
247
125
350
175
454
250
mV
VOS
Common Mode Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
1.125
1.25
1.375
V
RTERM
On-Chip Termination Resistance
Termination Enabled, OVDD =1.8V
100
Ω
DigiTal inpuTs anD ouTpuTs The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
poWer reQuireMenTs The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
LTC2268-14
LTC2267-14
LTC2266-14
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
VDD
Analog Supply Voltage (Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
OVDD
Output Supply Voltage (Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
IVDD
Analog Supply Current Sine Wave Input
l
150
168
119
131
98
111
mA
IOVDD
Digital Supply Current 2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
l
16
30
20
34
16
29
19
33
15
29
18
32
mA
PDISS
Power Dissipation
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
l
299
324
338
364
243
266
270
295
203
229
232
257
mW
PSLEEP
Sleep Mode Power
1
mW
PNAP
Nap Mode Power
70
mW
PDIFFCLK Power Increase with Differential Encode Mode Enabled
(No Increase for Sleep Mode)
20
mW
TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
LTC2268-14
LTC2267-14
LTC2266-14
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
fS
Sampling Frequency
(Notes 10, 11)
l
5
125
5
105
5
80
MHz
tENCL
ENC Low Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
3.8
2
4
100
4.52
2
4.76
100
5.93
2
6.25
100
ns
tENCH
Analog Supply Current
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
3.8
2
4
100
4.52
2
4.76
100
5.93
2
6.25
100
ns
tAP
Sample-and-Hold
Acquisition Delay Time
0
ns
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