For more information www.linear.com/LTC2262-12 Overflow Bit The overflow output " />
參數(shù)資料
型號(hào)： LTC2262IUJ-12#PBF
廠商： Linear Technology
文件頁數(shù)： 10/28頁
文件大小： 0K
描述： IC ADC 12BIT 150MSPS 40-QFN
產(chǎn)品培訓(xùn)模塊： LTC2262 - Ultra Low Power High Speed ADCs
標(biāo)準(zhǔn)包裝： 61
位數(shù)： 12
采樣率（每秒）： 150M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 146mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-QFN（6x6）
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)差分
配用： DC890B-ND - BOARD USB DATA COLLECTION
LTC2262-12
18
226212fc
For more information www.linear.com/LTC2262-12
Overflow Bit
The overflow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged.
The overflow bit has the same pipeline latency as the
data bits.
Phase Shifting the Output Clock
In full-rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT+,
so the rising edge of CLKOUT+ can be used to latch the
output data. In double data rate CMOS and LVDS modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT+. To allow adequate
setup-and-hold time when latching the data, the CLKOUT+
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
The LTC2262-12 can also phase shift the CLKOUT+/
CLKOUT– signals by serially programming mode con-
trol register A2. The output clock can be shifted by
0°, 45°, 90° or 135°. To use the phase shifting feature
the clock duty cycle stabilizer must be turned on.
Another control register bit can invert the polarity of
CLKOUT+ and CLKOUT–, independently of the phase shift.
The combination of these two features enables phase
shifts of 45° up to 315° (Figure 14).
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V RANGE)
OF
D11-D0
(OFFSET BINARY)
D11-D0
(2’s COMPLEMENT)
>+1.000000V
+0.999512V
+0.999024V
1
0
1111 1111 1111
1111 1111 1110
0111 1111 1111
0111 1111 1110
+0.000488V
0.000000V
–0.000488V
–0.000976V
0
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
–0.999512V
–1.000000V
≤–1.000000V
0
1
0000 0000 0001
0000 0000 0000
1000 0000 0001
1000 0000 0000
APPLICATIONS INFORMATION
CLKOUT+
D0-D11, OF
PHASE
SHIFT
0°
45°
90°
135°
180°
225°
270°
315°
CLKINV
0
1
CLKPHASE1
MODE CONTROL BITS
0
1
0
1
CLKPHASE0
0
1
0
1
0
1
0
1
226212 F14
ENC+
Figure 14. Phase Shifting CLKOUT
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LTC2262IUJ-14#PBF 制造商:Linear Technology 功能描述:ADC Single Pipelined 150Msps 14-bit Parallel/LVDS 40-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 14BIT 1.8V 150MSPS 40-QFN
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LTC2263-12 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 65Msps/40Msps/25Msps Low Power Dual ADCs
LTC2263-14 制造商:LINER 制造商全稱:Linear Technology 功能描述:Quad 14-Bit, 125Msps ADC with Integrated Drivers
LTC2263CUJ-12#PBF 功能描述:IC ADC 12BIT SER/PAR 25M 40-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6
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