參數(shù)資料
型號: LTC2261IUJ-12#PBF
廠商: Linear Technology
文件頁數(shù): 16/34頁
文件大?。?/td> 0K
描述: IC ADC 12-BIT 125MSPS 40-QFN
產品培訓模塊: LTC2262 - Ultra Low Power High Speed ADCs
標準包裝: 61
位數(shù): 12
采樣率(每秒): 125M
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 1
功率耗散(最大): 146mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應商設備封裝: 40-QFN(6x6)
包裝: 管件
輸入數(shù)目和類型: 1 個差分
配用: DC890B-ND - BOARD USB DATA COLLECTION
LTC2261-12
LTC2260-12/LTC2259-12
23
226112fc
For more information www.linear.com/LTC2261-12
Overflow Bit
The overflow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged. The
overflow bit has the same pipeline latency as the data bits.
Phase Shifting the Output Clock
In full-rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT+,
so the rising edge of CLKOUT+ can be used to latch the
output data. In double-data rate CMOS and LVDS modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT+. To allow adequate
setup-and-hold time when latching the data, the CLKOUT+
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
TheLTC2261-12/LTC2260-12/LTC2259-12canalsophase
shift the CLKOUT+/CLKOUTsignals by serially program-
ming mode control register A2. The output clock can be
shifted by 0°, 45°, 90° or 135°. To use the phase shifting
feature the clock duty cycle stabilizer must be turned
on. Another control register bit can invert the polarity of
CLKOUT+ and CLKOUT, independently of the phase shift.
Thecombinationofthesetwofeaturesenablesphaseshifts
of 45° up to 315° (Figure 14).
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V RANGE)
OF
D11-D0
(OFFSET BINARY)
D11-D0
(2’s COMPLEMENT)
>+1.000000V
+0.999512V
+0.999024V
1
0
1111 1111 1111
1111 1111 1110
0111 1111 1111
0111 1111 1110
+0.000488V
0.000000V
–0.000488V
–0.000976V
0
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
–0.999512V
–1.000000V
≤–1.000000V
0
1
0000 0000 0001
0000 0000 0000
1000 0000 0001
1000 0000 0000
applicaTions inForMaTion
CLKOUT+
D0-D11, OF
PHASE
SHIFT
45°
90°
135°
180°
225°
270°
315°
CLKINV
0
1
CLKPHASE1
MODE CONTROL BITS
0
1
0
1
CLKPHASE0
0
1
0
1
0
1
0
1
226112 F14
ENC+
Figure 14. Phase Shifting CLKOUT
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