參數資料
型號: LTC2237CUH#PBF
廠商: Linear Technology
文件頁數: 11/28頁
文件大小: 0K
描述: IC ADC 10-BIT 40MSPS 3V 32-QFN
標準包裝: 73
位數: 10
采樣率(每秒): 40M
數據接口: 并聯
轉換器數目: 1
功率耗散(最大): 144mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤
供應商設備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 管件
輸入數目和類型: 1 個單端,雙極; 1 個差分,雙極
LTC2238/LTC2237/LTC2236
19
223876fa
APPLICATIO S I FOR ATIO
WU
UU
Input Range
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise perfor-
mance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 0.6dB. See the Typical Performance Charac-
teristics section.
Driving the Clock Input
The CLK input can be driven directly with a CMOS or TTL
level signal. A sinusoidal clock can also be used along with
a low-jitter squaring circuit before the CLK pin (see
Figure 11).
The noise performance of the LTC2238/LTC2237/LTC2236
can depend on the clock signal quality as much as on the
analog input. Any noise present on the clock signal will
result in additional aperture jitter that will be RMS summed
with the inherent ADC aperture jitter.
In applications where jitter is critical, such as when digitiz-
ing high input frequencies, use as large an amplitude as
possible. Also, if the ADC is clocked with a sinusoidal
signal, filter the CLK signal to reduce wideband noise and
distortion products generated by the source.
Figures 12 and 13 show alternatives for converting a
differential clock to the single-ended CLK input. The use of
a transformer provides no incremental contribution to
phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz
will degrade the SNR compared to the transformer solu-
tion. The nature of the received signals also has a large
CLK
50
0.1
F
0.1
F
4.7
F
1k
FERRITE
BEAD
CLEAN
SUPPLY
SINUSOIDAL
CLOCK
INPUT
223876 F11
NC7SVU04
LTC2238
LTC2237
LTC2236
Figure 11. Sinusoidal Single-Ended CLK Drive
bearing on how much SNR degradation will be experi-
enced. For high crest factor signals such as WCDMA or
OFDM, where the nominal power level must be at least 6dB
to 8dB below full scale, the use of these translators will
have a lesser impact.
The transformer shown in the example may be terminated
with the appropriate termination for the signaling in use.
The use of a transformer with a 1:4 impedance ratio may
be desirable in cases where lower voltage differential
signals are considered. The center tap may be bypassed to
ground through a capacitor close to the ADC if the differ-
ential signals originate on a different plane. The use of a
capacitor at the input may result in peaking, and depend-
ing on transmission line length may require a 10
to 20
ohm series resistor to act as both a low pass filter for high
frequency noise that may be induced into the clock line by
neighboring digital signals, as well as a damping mecha-
nism for reflections.
CLK
100
0.1
F
4.7
F
FERRITE
BEAD
CLEAN
SUPPLY
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
223876 F12
LTC2238/
LTC2237/
LTC2236
CLK
5pF-30pF
ETC1-1T
0.1
F
VCM
FERRITE
BEAD
DIFFERENTIAL
CLOCK
INPUT
223876 F13
LTC2238/
LTC2237/
LTC2236
Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter
Figure 13. LVDS or PECL CLK Drive Using a Transformer
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