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參數(shù)資料
| 型號： | LTC2175IUKG-14#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 125MSPS QUAD 52QFN |
| 標準包裝： | 2,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | Serial LVDS |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 646mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 52-QFN（7x8） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 Differential; 2 Single-Ended |
| 配用： | DC1371A-ND - BOARD USB DATA ACQUISITION HS |
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LTC2175-14/
LTC2174-14/LTC2173-14
16
21754314fa
pin FuncTions
AIN1+ (Pin 1): Channel 1 Positive Differential Analog
Input.
AIN1–(Pin2):Channel1NegativeDifferentialAnalogInput.
VCM12 (Pin 3): Common Mode Bias Output, Nominally
Equal to VDD/2. VCM should be used to bias the common
mode of the analog inputs of channels 1 and 2. Bypass
to ground with a 0.1F ceramic capacitor.
AIN2+ (Pin 4): Channel 2 Positive Differential Analog
Input.
AIN2–(Pin5):Channel2NegativeDifferentialAnalogInput.
REFH (Pins 6,7): ADC High Reference. Bypass to pins 8, 9
with a 2.2F ceramic capacitor and to ground with a 0.1F
ceramic capacitor.
REFL (Pins 8,9): ADC Low Reference. Bypass to pins 6, 7
with a 2.2F ceramic capacitor and to ground with a 0.1F
ceramic capacitor.
AIN3+(Pin10):Channel3PositiveDifferentialAnalogInput.
AIN3–(Pin11):Channel3NegativeDifferentialAnalogInput.
VCM34 (Pin 12): Common Mode Bias Output, Nominally
Equal to VDD/2. VCM should be used to bias the common
mode of the analog inputs of channels 3 and 4. Bypass
to ground with a 0.1F ceramic capacitor.
AIN4+(Pin13):Channel4PositiveDifferentialAnalogInput.
AIN4–(Pin14):Channel4NegativeDifferentialAnalogInput.
VDD (Pins 15, 16, 51, 52): 1.8V Analog Power Supply.
Bypass to ground with 0.1F ceramic capacitors. Adjacent
pins can share a bypass capacitor.
ENC+ (Pin 17): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 18): Encode Complement Input. Conversion
starts on the falling edge.
CS (Pin 19): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When CS is
low, SCK is enabled for shifting data on SDI into the mode
controlregisters.Intheparallelprogrammingmode(PAR/
SER = VDD), CS selects 2-lane or 1-lane output mode. CS
can be driven with 1.8V to 3.3V logic.
SCK (Pin 20): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = VDD), SCK selects 3.5mA
or 1.75mA LVDS output currents. SCK can be driven with
1.8V to 3.3V logic.
SDI (Pin 21): In serial programming mode, (PAR/SER =
0V), SDI is the serial interface data Input. Data on SDI is
clocked into the mode control registers on the rising edge
of SCK. In the parallel programming mode (PAR/SER =
VDD), SDI can be used to power down the part. SDI can
be driven with 1.8V to 3.3V logic.
GND (Pins 22, 45, 49): ADC Power Ground.
OGND (Pin 33): Output Driver Ground. Must be shorted
to the ground plane by a very low inductance path. Use
multiple vias close to the pin.
OVDD (Pin 34): Output Driver Supply. Bypass to ground
with a 0.1F ceramic capacitor.
SDO (Pin 46): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control regis-
ters and can be latched on the falling edge of SCK. SDO
is an open-drain NMOS output that requires an external
2k pull-up resistor to 1.8V – 3.3V. If read back from the
mode control registers is not needed, the pull-up resistor
is not necessary and SDO can be left unconnected. In the
parallel programming mode (PAR/SER = VDD), SDO is an
input that enables internal 100 termination resistors on
the digital outputs. When used as an input, SDO can be
driven with 1.8V to 3.3V logic through a 1k series resistor.
PAR/SER (Pin 47): Programming Mode Selection Pin.
Connecttogroundtoenabletheserialprogrammingmode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to VDD to enable the
parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or the VDD of the part and not be driven
by a logic signal.
VREF(Pin48):ReferenceVoltageOutput.Bypasstoground
with a 1F ceramic capacitor, nominally 1.25V.
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