參數(shù)資料
型號(hào)： LTC1867LIGN#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 5/16頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT 8CH 175KSPS 16SSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 16
采樣率（每秒）： 175k
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 2.7mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)差分，單極；4 個(gè)差分，雙極
配用： DC873A-ND - BOARD SAR ADC LTC1867L
DC806A-ND - BOARD SAR ADC LTC1867
LTC1863L/LTC1867L
13
1863l7lfc
APPLICATIONS INFORMATION
If the CS/CONV returns low during a bit decision, it can
create a small error. For best performance ensure that the
CS/CONV returns low either within 100ns after the conver-
sion starts (i.e. before the rst bit decision) or after the
conversion ends. If CS/CONV is low when the conversion
ends, the MSB bit will appear on SDO at the end of the
conversion and the ADC will remain powered up.
Sleep Mode
If the SLP = 1 is selected in the input word, the ADC will
enter SLEEP mode and draw only leakage current (pro-
vided that all the digital inputs stay at GND or VDD). After
release from the SLEEP mode, the ADC needs 80ms to
wake up (charge the 2.2μF/10μF bypass capacitors on
VREF/REFCOMP pins).
Board Layout and Bypassing
To obtain the best performance, a printed circuit board
with a ground plane is required. Layout for the printed
circuit board should ensure digital and analog signal lines
are separated as much as possible. In particular, care
should be taken not to run any digital signal alongside
an analog signal.
All analog inputs should be screened by GND. VREF, REF-
COMP and VDD should be bypassed to this ground plane
as close to the pin as possible; the low impedance of the
common return for these bypass capacitors is essential
to the low noise operation of the ADC. The width for these
tracks should be as wide as possible.
Timing and Control
Conversion start is controlled by the CS/CONV digital in-
put. The rising edge transition of the CS/CONV will start a
conversion. Once initiated, it cannot be restarted until the
conversion is complete. Figures 6 and 7 show the timing
diagrams for two types of CS/CONV pulses.
Example 1 (Figure 6) shows the LTC1863L/LTC1867L
operating in automatic nap mode with CS/CONV signal
staying HIGH after the conversion. Automatic nap mode
provides power reduction at reduced sample rate.
The ADCs can also operate with the CS/CONV signal
returning LOW before the conversion ends. In this mode
(Example 2, Figure 7), the ADCs remain powered up. The
digital output, SDO, will go HIGH immediately after the
conversion is complete if the analog inputs are above
half scale in unipolar mode or below half scale in bipolar
mode. This is a way to measure the conversion time of
the A/D converter.
For best performance, it is recommended to keep SCK, SDI,
and SDO at a constant logic high or low during acquisition
and conversion, even though these signals may be ignored
by the serial interface (DON’T CARE). Communication
with other devices on the bus should not coincide with
the conversion period (tCONV).
Figures 8 and 9 are the transfer characteristics for the
bipolar and unipolar mode.
S0
SD
0S
S1
COM UNI
SLP
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1/fSCK
tACQ
CS/CONV
SCK
SDI
SDO
(LTC1863)
Hi-Z
D12
D15
D14
D13
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
123456789
10
11
12
13
14
15
16
1863L7L F06
DON'T CARE
NOT NEEDED FOR LTC1863
tCONV
NAP MODE
SDO
(LTC1867)
MSB
DON'T CARE
Figure 6. Example 1, CS/CONV Starts a Conversion and Remains HIGH Until Next Data Transfer. With CS/CONV
Remaining HIGH After the Conversion, Automatic Nap Modes Provides Power Reduction at Reduced Sample Rate
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