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參數資料
| 型號： | LTC1850CFW#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數： | 10/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 1.25MSPS 48-TSSOP |
| 標準包裝： | 1,800 |
| 位數： | 10 |
| 采樣率（每秒）： | 1.25M |
| 數據接口： | 并聯(lián) |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應商設備封裝： | 48-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 8 個單端，單極；8 個單端，雙極；4 個差分，單極；4 個差分，雙極 |
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18
LTC1850/LTC1851
18501f
APPLICATIO S I FOR ATIO
WU
UU
as free of breaks and holes as possible, such that a low
impedance path between all ADC grounds and all ADC
decoupling capacitors is provided. It is critical to prevent
digital noise from being coupled to the analog inputs,
reference or analog power supply lines. Layout for the
printed circuit board should ensure that digital and analog
signal lines are separated as much as possible. In particu-
lar, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 34 (OGND), Pin 13 (GND), Pin 16 (ADC’s GND) and all
other analog grounds should be connected to this single
analog ground point. The bypass capacitors should also
be connected to this analog ground plane. No other digital
grounds should be connected to this analog ground plane.
In some applications, it may be desirable to connect the
OVDD to the logic system supply and OGND to the logic
system ground. In these cases, OVDD should be bypassed
to OGND instead of the analog ground plane.
Low impedance analog and digital power supply common
returns are essential to the low noise operation of the ADC
and the foil width for these tracks should be as wide as
possible. In applications where the ADC data outputs and
control signals are connected to a continuously active
microprocessor bus, it is possible to get errors in the
conversion results. These errors are due to feedthrough
from the microprocessor to the successive approximation
comparator. The problem can be eliminated by forcing the
microprocessor into a WAIT state during conversions or
by using three-state buffers to isolate the ADC bus. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
The LTC1850/LTC1851 have differential inputs to mini-
mize noise coupling. Common mode noise on the “+” and
“–” inputs will be rejected by the input CMRR. The LTC1850/
LTC1851 will hold and convert the difference between
whichever input is selected as the “+” input and whichever
input is selected as the “–” input. Leads to the inputs
should be kept as short as possible.
SINGLE-ENDED/
DIFFERENTIAL BIT
UNIPOLAR/
BIPOLAR BIT
S6
S5
A2
A0
END OF
SEQUENCE BIT
PGA BIT
1851 F01
A1
MUX ADDRESS
S4
S3
S2
S1
S0
Figure 1. Readback Status Word
Unipolar Transfer Characteristic
(UNI/BIP = 0)
Bipolar Transfer Characteristic
(UNI/BIP = 1)
INPUT VOLTAGE (V)
0
FS – 1LSB
OUTPUT
CODE
1111...1111
1111...1110
1111...1101
1000...0001
1000...0000
0111...1111
0111...1110
0000...0010
0000...0001
0000...0000
1851 F01A
FS = VREFCOMP
INPUT VOLTAGE (V)
– FS
–1LSB 0 1LSB
FS – 1LSB
OUTPUT
CODE
0111...1111
0111...1110
0111...1101
0000...0001
0000...0000
1111...1111
1111...1110
1000...0010
1000...0001
1000...0000
1851 F01B
BIPOLAR
ZERO
FS =
VREFCOMP
2
BOARD LAYOUT AND BYPASSING
To obtain the best performance from the LTC1850/
LTC1851, a printed circuit board with ground plane is
required. The ground plane under the ADC area should be
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