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參數(shù)資料
| 型號： | LTC1743IFW |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 50MSPS SMPL 48TSSOP |
| 標(biāo)準(zhǔn)包裝： | 39 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 50M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.2W |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
12
LTC1743
1743f
APPLICATIO S I FOR ATIO
WU
U
Aperture Delay Time
The time from when a rising ENC equals the ENC voltage
to the instant that the input signal is held by the sample and
hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π) FIN TJITTER
CONVERTER OPERATION
As shown in Figure 1, the LTC1743 is a CMOS pipelined
multistep converter. The converter has four pipelined ADC
stages; a sampled analog input will result in a digitized
value five cycles later, see the Timing Diagram section.
The analog input is differential for improved common
mode noise immunity and to maximize the input range.
Additionally, the differential input drive will reduce even
order harmonics of the sample-and-hold circuit. The en-
code input is also differential for improved common mode
noise immunity.
The LTC1743 has two phases of operation, determined by
the state of the differential ENC/ENC input pins. For brev-
ity, the text will refer to ENC greater than ENC as ENC high
and ENC less than ENC as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and visa versa.
INTERNAL
CLOCK SIGNALS
INTERNAL
REFERENCES TO ADC
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
RANGE
SELECT
2.5V
REFERENCE
ENC
OUTPUT
DRIVERS
SHIFT REGISTER AND CORRECTION
OE
MSBINV
OGND
OF
OVDD
0.5V TO
5V
D11
D0
CLKOUT
1743 F01
INPUT
S/H
FIRST STAGE
SENSE
VCM
AIN
–
AIN
+
4.7
F
SECOND STAGE
THIRD STAGE
FOURTH STAGE
5-BIT
PIPELINED
ADC STAGE
4-BIT
PIPELINED
ADC STAGE
4-BIT
PIPELINED
ADC STAGE
2-BIT
FLASH
ADC
CONTROL
LOGIC
REFLA
REFHB
4.7
F
1
F1F
0.1
F
0.1
F
REFHA
REFLB
REF
BUF
DIFF
REF
AMP
Figure 1. Functional Block Diagram
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