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參數資料
| 型號： | LTC1741IFW |
| 廠商： | Linear Technology |
| 文件頁數： | 4/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC SMPL 12BIT 65MSPS 48TSSOP |
| 標準包裝： | 39 |
| 位數： | 12 |
| 采樣率（每秒）： | 65M |
| 數據接口： | 并聯 |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 1.38W |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應商設備封裝： | 48-TSSOP |
| 包裝： | 管件 |
| 輸入數目和類型： | 2 個單端，雙極；1 個差分，雙極 |
12
LTC1741
1741f
time. If the change between the last sample and the new
sample is small the charging glitch seen at the input will be
small. If the input change is large, such as the change seen
with input frequencies near Nyquist, then a larger charging
glitch will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential drive
to achieve specified performance. Each input should swing
±0.8V for the 3.2V range or ±0.5V for the 2V range, around
a common mode voltage of 2.35V. The VCM output pin
(Pin 2) may be used to provide the common mode bias level.
VCM can be tied directly to the center tap of a transformer
to set the DC input level or as a reference level to an op amp
differential driver circuit. The VCM pin must be bypassed to
ground close to the ADC with a 4.7
F or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs the dy-
namic performance of the LTC1741 can be influenced by
the input drive circuitry, particularly the second and third
harmonics. Source impedance and input reactance can
influence SFDR. At the falling edge of encode the sample-
and-hold circuit will connect the 4pF sampling capacitor to
the input pin and start the sampling period. The sampling
period ends when encode rises, holding the sampled input
on the sampling capacitor. Ideally the input circuitry
should be fast enough to fully charge the sampling capaci-
tor during the sampling period 1/(2FENCODE); however,
this is not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recomended to have a
source impedence of 100
or less for each input. The S/H
circuit is optimized for a 50
source impedance. If the
source impedance is less than 50
, a series resistor
should be added to increase this impedance to 50
. The
source impedence should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC1741 being driven by an RF
transformer with a center tapped secondary. The second-
ary center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used if the
source impedence seen by the ADC does not exceed
100
for each ADC input. A disadvantage of using a
transformer is the loss of low frequency response. Most
small RF transformers have poor performance at frequen-
cies below 1MHz.
APPLICATIO S I FOR ATIO
WU
UU
1:1
25
0.1
F
ANALOG
INPUT
VCM
AIN
+
AIN
–
100
100
12pF
1741 F03
4.7
F
25
25
25
LTC1741
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
Figure 4 demonstrates the use of operational amplifiers to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain band-
width of most op amps will limit the SFDR at high input
frequencies.
The 25
resistors and 12pF capacitors on the analog
inputs serve two purposes: isolating the drive circuitry
from the sample-and-hold charging glitches and limiting
the wideband noise at the converter input. For input
frequencies higher than 100MHz, the capacitors may need
to be decreased to prevent excessive signal loss.
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