參數(shù)資料
型號: LTC1741IFW#TR
廠商: Linear Technology
文件頁數(shù): 5/20頁
文件大?。?/td> 0K
描述: IC ADC SMPL 12BIT 65MSPS 48TSSOP
標(biāo)準(zhǔn)包裝: 1,800
位數(shù): 12
采樣率(每秒): 65M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.38W
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,雙極;1 個差分,雙極
13
LTC1741
1741f
Reference Operation
Figure 5 shows the LTC1741 reference circuitry consisting
of a 2.35V bandgap reference, a difference amplifier and
switching and control circuit. The internal voltage refer-
ence can be configured for two pin selectable input ranges
of 2V(
±1V differential) or 3.2V(±1.6V differential). Tying
the SENSE pin to ground selects the 2V range; tying the
SENSE pin to VDD selects the 3.2V range.
The 2.35V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to gener-
ate the differential reference levels needed by the internal
ADC circuitry.
An external bypass capacitor is required for the 2.35V
reference output, VCM. This provides a high frequency low
impedance path to ground for internal and external cir-
cuitry. This is also the compensation capacitor for the
reference. It will not be stable without this capacitor.
The difference amplifier generates the high and low refer-
ence for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins: REFHA and REFHB
for the high reference and REFLA and REFLB for the low
reference. The doubled output pins are needed to reduce
package inductance. Bypass capacitors must be con-
nected as shown in Figure 5.
Other voltage ranges in between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 6a. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device since the logic threshold is close to ground and
VDD. The SENSE pin should be tied high or low as close to
the converter as possible. If the SENSE pin is driven
externally, it should be bypassed to ground as close to the
device as possible with a 1
F ceramic capacitor.
Input Range
The input range can be set based on the application. For
oversampled signal processing in which the input fre-
quency is low (<10MHz), the largest input range will
provide the best signal-to-noise performance while main-
taining excellent SFDR. For high input frequencies
(> 40MHz), the 2V range will have the best SFDR perfor-
mance for the 2nd and 3rd harmonics, but the SNR will
degrade by 1.5dB. See the Typical Performance Charac-
teristics section.
APPLICATIO S I FOR ATIO
WU
UU
25
5V
SINGLE-ENDED
INPUT
2.35V
±1/2
RANGE
VCM
AIN
+
AIN
12pF
1741 F04
4.7
F
25
100
500
500
25
25
LTC1741
+
1/2 LT1810
+
1/2 LT1810
Figure 4. Differential Drive with Op Amps
VCM
REFHA
REFLB
SENSE
TIE TO VDD FOR 3.2V RANGE;
TIE TO GND FOR 2V RANGE;
RANGE = 2 VSENSE FOR
1V < VSENSE < 1.6V
2.35V
REFLA
REFHB
4.7
F
4.7
F
INTERNAL ADC
HIGH REFERENCE
BUFFER
0.1
F
1741 F05
LTC1741
4
DIFF AMP
1
F
1
F
0.1
F
INTERNAL ADC
LOW REFERENCE
2.35V BANDGAP
REFERENCE
1.6V
1V
RANGE
DETECT
AND
CONTROL
Figure 5. Equivalent Reference Circuit
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