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參數(shù)資料
| 型號： | LTC1710CMS8 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Dual 16-By-4 Register Files 24-SOIC 0 to 70 |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封裝： | PLASTIC, MSOP-8 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 219K |
| 代理商： | LTC1710CMS8 |
6
LTC1710
OPERATIOU
The master then sends out the first byte. The first seven
bits of this byte consist of the address of the device that the
master wishes to communicate with. The last bit indicates
whether the command will be a read (logic one) or write
(logic zero). Because the LTC1710 is a slave device that
can only be written to by a master, it will ignore the ensuing
commands of the master if it wants to read from the
LTC1710, even if the address sent by the master matches
that of the LTC1710. After reception of the first byte, the
slave device (LTC1710) with the matching address then
acknowledges the master by pulling the DATA line low
before the next rising clock edge.
By now all other nonmatching slave devices will have gone
back to their original standby states to wait for the next
Start signal. Meanwhile, upon receiving the acknowledge
from the matching slave, the master then sends out the
command byte (see Table 1).
Table 1. Switch Control Table
COMMAND
XXXXXX00
Switch 0
Switch 1
XXXXXX01
SW0 On
SW1 Off
XXXXXX10
SW0 Off
SW1 On
XXXXXX11
SW0 On
SW1 On
SW0 Off
SW1 Off
After receiving the command byte, the slave device
(LTC1710) needs to acknowledge the master again by
pulling the DATA line low on the following clock cycle. The
master then ends this Send Byte Protocol by sending the
Stop signal, which is a transition from low to high on the
DATA line while the CLK line is high. Valid data is shifted
into the output latch on the last acknowledge signal; the
output switch will not turn on, however, until the Stop
signal is detected. This double buffering feature of the
output latch allows the user to “daisy-chain” multiple
SMBus devices such that their outputs are synchronously
executed on the Stop signal despite the fact that valid data
were loaded into their output latches at different times. An
example is shown in Figure 1. If somehow either the Start
or the Stop signal is detected in the middle of a byte, the
slave device (LTC1710) will regard this as an error and
reject all previous data.
Address
The LTC1710 has an address of 10110XX; the five MSBs
are hardwired, but the two LSBs are programmable by the
user with the help of a three-state address pin. Refer to
Table 2 for the pin configurations and their corresponding
addresses.
Table 2. Address Pin Truth Table
AD1
GND
V
CC
/2
V
CC
ADDRESS
1011000
1011001
1011010
To conserve standby current, it is preferable to tie the
address pins to either V
CC
or GND. If three LTC1710s are
needed, then the address pin can be tied to the third state
of V
CC
/2 by using two equal value resistors (
≤
1M), see
Figure 2.
CLK
DATA
ACK
1710 TA03
1
(SW0
ON)
1
(SW1
ON)
0
0
0
0
0
0
0
0
(PROGRAMMABLE)
1
1
0
1
START
0
ACK
0
(WRITE)
STOP
ADDRESS BYTE
COMMAND BYTE
Figure 2. The LTC1710 Programmed with Address 1011001
START ADDR1
ADDR2
COMMAND
COMMAND
A
START
START
A
A
A
A
A
ADDR3
COMMAND
EXECUTION OF DATA STORED IN
OUTPUT LATCH OF DEVICES WITH
ADDR1, ADDR2 AND ADDR3
STOP
1710 F01
Figure 1. Daisy-Chain Example
5
3
6
4
1
2
1M
5V
8
7
1710 F02
DATA
CLK
AD1
SW0D
OUT0
V
CC
LTC1710
OUT1
GND
LOAD 1
LOAD 2
1M
Example of Send Byte Protocol to Slave Address 1011000 Turning SW0 and SW1 On
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