參數(shù)資料
型號(hào)： LTC1705EGN
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： Dual 550kHz Synchronous Switching Regulator Controller with 5-Bit VID and 150mA LDO
中文描述： 5 A DUAL SWITCHING CONTROLLER, 650 kHz SWITCHING FREQ-MAX, PDSO28
封裝： 0.150 INCH, PLASTIC, SSOP-28
文件頁(yè)數(shù)： 12/28頁(yè)
文件大?。?/td> 326K
代理商： LTC1705EGN
LTC1705
12
APPLICATIU
W
U
U
High Efficiency
The LTC1705 core and I/O supplies use a synchronous
step-down (buck) architecture, with two external N-chan-
nel MOSFETs per output. A floating topside driver and a
simple external charge pump provide full gate drive to
each upper MOSFET. The voltage mode feedback loops
and MOSFET V
DS
current limit sensing circuits remove the
need for external current sense resistors, eliminating
external components and the corresponding power losses
in the high current paths. Properly designed circuits using
low gate charge MOSFETs are capable of efficiencies
exceeding 90% over a wide range of output voltages and
load currents.
VID Programming
The LTC1705 includes an onboard feedback network that
programs the core output voltage in accordance with the
Intel Mobile VID specification (Table 1). This network
includes a 10k resistor connected between SENSEC and
FBC and a variable value resistor connected between FBC
and GND, with the value set by the digital code present at
the VID4:0 pins. Connect SENSEC to V
OUTC
to allow the
network to monitor the output voltage. No additional
feedback components are required to set the output volt-
age of the core controller, although loop compensation
components are still required. Each VIDnpin includes an
internal 30k pull-up resistor, allowing it to float high if left
unconnected. The pull-up resistors connect to V
CC
through
diodes (see Block Diagram), allowing the VIDnpins to be
pulled above V
CC
without damage.
Note that codes 01111 and 11111, defined by Intel to
indicate “no CPU present, ” do generate output voltages at
V
OUTC
(1.25V and 0.9V, respectively). Also, note that the
I/O and CLK outputs on the LTC1705 are not connected to
the VID circuitry and work independently from the core
controller.
Linear Regulator and Thermal Shutdown
The LTC1705 CLK output is an easy to use monolithic LDO.
The V
INCLK
pin powers the regulator and an internal
P-channel MOS transistor provides the output current at
the 2.5V output. An external 10
μ
F capacitor frequency
compensates the linear regulator feedback loop. The CLK
output is short-circuit protected and the built-in thermal
shutdown circuit turns off all three regulator outputs
should the LTC1705 junction temperature exceed 155
°
C.
SWITCHING ARCHITECTURE DETAILS
The LTC1705 dual switching regulator controller includes
two independent regulator channels. The two switching
regulator controllers and their corresponding external
components act independently of each other with the
exception of the common input bypass capacitor. The
RUN/SS and PGOOD pins also affect both channels. In the
following discussions, when a pin is referred to without
mentioning which side is involved, that discussion applies
equally to both sides.
Switching Architecture
Each half of the LTC1705 is designed to operate as a
synchronous buck converter (Figure 1). Each channel
includes two high power MOSFET gate drivers to control
external N-channel MOSFETs QT and QB. The core drivers
have 0.5
output impedances and can carry well over an
amp of continuous current with peak currents up to 5A to
slew large MOSFET gates quickly. The I/O drivers have 2
output impedances. The external MOSFETs are connected
with the drain of QT attached to the input supply and the
source of QT at the switching node SW. QB is the synchro-
nous rectifier with its drain at SW and its source at PGND.
SW is connected to one end of the inductor, with the other
end connected to V
OUT
. The output capacitor is connected
from V
OUT
to PGND.
When a switching cycle begins, QB is turned off and QT is
turned on. SW rises almost immediately to V
IN
and the
inductor current begins to increase. When the PWM pulse
finishes, QT turns off and one nonoverlap interval later, QB
turns on. Now SW drops to PGND and the inductor current
decreases. The cycle repeats with the next tick of the
master clock. The percentage of time spent in each mode
is controlled by the duty cycle of the PWM signal, which in
turn is controlled by the feedback amplifier. The master
clock runs at a 550kHz rate and turns QT on once every
1.8
μ
s. In a typical application with a 5V input and a 1.5V
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