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參數(shù)資料
| 型號： | LTC1668 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 16-Bit, 50Msps Differential Current OutputDAC(16位，50Msps，差分電流輸出數(shù)模轉(zhuǎn)換器) |
| 中文描述： | 16位，50 MSPS的差分電流OutputDAC（16位，50 MSPS的，差分電流輸出數(shù)模轉(zhuǎn)換器） |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 732K |
| 代理商： | LTC1668 |
9
LTC1668
APPLICATIOU
resistance on I
OUT A
and I
OUT B
is equivalent to a single
differential resistor of 50
, and the 1:1 turns ratio means
the output impedance from the transformer is 50
. Note
that the load resistors are optional, and they dissipate half
of the output power. However, in lab environments or
when driving long transmission lines it is very desirable to
have a 50
output impedance. This could also be done
with a 50
resistor at the transformer secondary, but
putting the load resistors on I
OUT A
and I
OUT B
is preferred
since it reduces the current through the transformer. At
signal frequencies lower than about 1MHz, the trans-
former core size required to maintain low distortion gets
larger, and at some lower frequencies this becomes
impractical.
A differential resistor loaded output configuration is shown
in the Block Diagram. It is simple and economical, but it
can drive only differential loads with impedance levels and
amplitudes appropriate for the DAC outputs.
The recommended single-ended resistor loaded configu-
ration is essentially the same circuit as the differential
resistor loaded, case—simply use the I
OUT A
output,
referred to ground. Rather than tying the unused I
OUT B
output to ground, it is preferred to load it with the equiva-
lent R
LOAD
of I
OUT A
. Then I
OUT B
will still swing with a
waveform complementary to I
OUT A
.
Adding an op amp differential to single-ended converter
circuit to the differential resistor loaded output gives the
circuit of Figure 10.
This circuit complements the capabilities of the trans-
former-coupled application at lower frequencies, since
available op amps can deliver good AC distortion perfor-
mance at signal frequencies of a few MHz down to DC. The
optional capacitor adds a single real pole of filtering, and
helps reduce distortion by limiting the high frequency
signal amplitude at the op amp inputs. The circuit swings
±
1V around ground.
Figure 3 shows a simplified circuit for a single-ended
output using I-to-V converter to produce a unipolar
buffered voltage output. This configuration typically has
the best DC linearity performance, but its AC distortion at
higher frequencies is limited by U1’s slewing capabilities.
W
U
U
200
1668 F03
I
OUT A
I
OUT B
LADCOM
LTC1668
R
FB
200
V
OUT
0V TO 2V
I
10mA
C
OUT
–
+
U1
LT
1812
Figure 3. Unipolar Buffered Voltage Output
Digital Interface
The LTC1668 has 16 parallel inputs that are latched on the
rising edge of the clock input. They accept CMOS levels
from either 5V or 3.3V logic and can accept clock rates of
up to 50MHz.
Referring to the Timing Diagram and Block Diagram, the
data inputs go to master-slave latches that update on the
rising edge of the clock. The input logic thresholds, V
IH
=
2.4V min, V
IL
= 0.8V max, work with 3.3V or 5V CMOS
levels over temperature. The guaranteed setup time, t
DS
,
is 8ns minimum and the hold time, t
DH
, is 4ns minimum.
The minimum clock high and low times are guaranteed at
6ns and 8ns, respectively. These specifications allow the
LTC1668 to be clocked at up to 50Msps minimum.
For best AC performance, the data and clock waveforms
need to be clean and free of undershoot and overshoot.
Clock and data interconnect lines should be twisted pair,
coax or microstrip, and proper line termination is impor-
tant. If the digital input signals to the DAC are considered
as analog AC voltage signals, they are rich in spectral
components over a broad frequency range, usually in-
cluding the output signal band of interest. Therefore, any
direct coupling of the digital signals to the analog output
will produce spurious tones that vary with the exact digital
input pattern.
Clock jitter should be minimized to avoid degrading the
noise floor of the device in AC applications, especially
where high output frequencies are being generated. Any
noise coupling from the digital inputs to the clock input will
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