參數(shù)資料
型號: LTC1667CG
廠商: LINEAR TECHNOLOGY CORP
元件分類: DAC
英文描述: 12-Bit, 14-Bit, 16-Bit, 50Msps DACs
中文描述: PARALLEL, WORD INPUT LOADING, 0.02 us SETTLING TIME, 14-BIT DAC, PDSO28
封裝: 5.30 MM, PLASTIC, SSOP-28
文件頁數(shù): 13/24頁
文件大?。?/td> 888K
代理商: LTC1667CG
13
LTC1666/LTC1667/LTC1668
APPLICATIOU
W
U
U
LADCOM
The LADCOM pin is the common connection for the
internal DAC attenuator ladder. It usually is tied to analog
ground, but more generally it should connect to the same
potential as the load resistors on I
OUT A
and I
OUT B
. The
LADCOM pin carries a constant current to V
SS
of approxi-
mately 0.32 (I
OUTFS
), plus any current that flows from
I
OUT A
and I
OUT B
through the R
IOUT A
and R
IOUT B
resistors.
Output Compliance
The specified output compliance voltage range is
±
1V. The
DC linearity specifications, INL and DNL, are trimmed and
guaranteed on I
OUT A
into the virtual ground of an
I-to-V converter, but are typically very good over the full
output compliance range. Above 1V the output current will
start to increase as the DAC current steering switch
impedance decreases, degrading both DC and AC linear-
ity. Below –1V, the DAC switches will start to approach the
transition from saturation to linear region. This will de-
grade AC performance first, due to nonlinear capacitance
and increased glitch impulse. AC distortion performance
is optimal at amplitudes less than
±
0.5V
P-P
on I
OUT A
and
I
OUT B
due to nonlinear capacitance and other large-signal
effects. At first glance, it may seem counter-intuitive to
decrease the signal amplitude when trying to optimize
SFDR. However, the error sources that affect AC perfor-
mance generally behave as additive currents, so decreas-
ing the load impedance to reduce signal voltage amplitude
will reduce most spurious signals by the same amount.
Figure 4. AC Characterization Setup (LTC1668)
+
16-BIT
HIGH SPEED
DAC
HP1663EA
LOGIC ANALYZER WITH
PATTERN GENERATOR
V
SS
V
DD
–5V
LADCOM
AGND
DGND
CLK
DB15
DB0
16
DIGITAL
DATA
CLK
IN
1666/7/8 F05
I
OUT A
0.1
μ
F
LTC1668
5V
I
REFIN
REFOUT
COMP1
COMP2
C2
0.1
μ
F
0.1
μ
F
OUT 1 OUT 2
C1
0.1
μ
F
R
SET
2k
I
OUT B
HP8110A DUAL
PULSE GENERATOR
LOW JITTER
CLOCK SOURCE
CLK
IN
50
0.1
μ
F
50
TO HP3589A
SPECTRUM
ANALYZER
50
INPUT
110
MINI-CIRCUITS
T1–1T
2.5V
REFERENCE
Figure 3. Equivalent Analog Output Circuit
20
19
23
18
R
IOUT B
5pF
5pF
–5V
1666/7/8
F04
R
1.1k
LADCOM
I
OUT A
I
OUT B
V
SS
52.3
52.3
LTC1666/LTC1667/LTC1668
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相關代理商/技術參數(shù)
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