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參數(shù)資料
| 型號： | LTC1654 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Dual 14-Bit Rail-to-Rail DAC in 16-Lead SSOP Package(雙路14位,滿幅度電壓輸出數(shù)模轉(zhuǎn)換器(16腳SSOP封裝)) |
| 中文描述： | 雙14位軌至軌DAC，采用16引線SSOP封裝（雙路14位，滿幅度電壓輸出數(shù)模轉(zhuǎn)換器（16腳SSOP封裝封裝）） |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 195K |
| 代理商： | LTC1654 |
12
LTC1654
Figure 1. Effect of Negative Offset
Zero-Scale Error (ZSE):
The output voltage when the
DAC is loaded with all zeros. Since this is a single supply
part, this value cannot be less than 0V.
Integral Nonlinearity (INL):
End-point INL is the maxi-
mum deviation from a straight line passing through the
end points of the DAC transfer curve. Because the part
operates from a single supply and the output cannot go
below zero, the linearity is measured between full scale
and the code corresponding to the maximum offset
specification. The INL error at a given input code is
calculated as follows:
INL
= [V
OUT
– V
OS
– (V
FS
– V
OS
)(code/16383)]/LSB
V
OUT
= The output voltage of the DAC measured at the
given input code
Differential Nonlinearity (DNL):
DNL is the difference
between the measured change and the ideal one LSB
change between any two adjacent codes. The DNL error
between any two codes is calculated as follows:
DNL
= (
V
OUT
– LSB)/LSB
V
OUT
= The measured voltage difference between
two adjacent codes
Digital Feedthrough:
The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
nV s.
Resolution (n):
Resolution is defined as the number of
digital input bits (n). It is also the number of DAC output
states (2
n
) that divide the full-scale range. Resolution does
not imply linearity.
Full-Scale Voltage (V
FS
):
This is the output of the DAC
when all bits are set to 1.
Voltage Offset Error (V
OS
):
Normally, DAC offset is the
voltage at the output when the DAC is loaded with all zeros.
The DAC can have a true negative offset, but because the
part is operated from a single supply, the output cannot go
below 0V. If the offset is negative, the output will remain
near 0V resulting in the transfer curve shown in Figure 1.
The offset of the part is measured at the code that corre-
sponds to the maximum offset specification:
V
OS
= V
OUT
– [(Code)(V
FS
)/(2
n
– 1)]
Least Significant Bit (LSB):
One LSB is the ideal voltage
difference between two successive codes.
LSB = (V
FS
– V
OS
)/(2
n
– 1) = (V
FS
– V
OS
)/16383
Nominal LSBs:
LTC1654 LSB = 4.09575V/16383 = 250
μ
V
DAC CODE
1654 F01
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
DEFU
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| LTC1655L | 16-Bit Rail-to-Rail Micropower DACs in SO-8 Package(16位,微功耗滿幅度電壓輸出數(shù)模轉(zhuǎn)換器(SO-8封裝,內(nèi)部基準(zhǔn)1.25V)) |
| LTC1657 | Parallel 16-Bit Rail-to-Rail Micropower DAC(并行16位,微功耗滿幅度電壓輸出數(shù)模轉(zhuǎn)換器) |
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| LTC1659 | 12-Bit Rail-to-Rail Micropower DAC in MSOP Package(12位,微功耗滿幅度電壓輸出數(shù)模轉(zhuǎn)換器（8腳MSOP封裝）) |
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| LTC1654CGN#PBF | 功能描述:IC D/A CONV 14BIT R-R DUAL16SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
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| LTC1654CGN#TRPBF | 功能描述:IC D/A CONV 14BIT R-R DUAL16SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
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