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參數(shù)資料
| 型號： | LTC1598LCG#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 3V 8CH SAMPL 24SSOP |
| 標準包裝： | 1,800 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 10.5k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 480µW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極 |
11
LTC1594L/LTC1598L
15948lfb
APPLICATIONS INFORMATION
WU
U
Figure 2. LTC1594L/LTC1598L Operating Sequence Example: All Channels Off
CLK
EN
D1
D2
tCYC
Hi-Z
DOUT
CH0 TO
CH7
DIN
tCONV
Hi-Z
tsuCS
NULL
BIT
D0
tOFF
D0N‘T CARE
ADCIN =
MUXOUT
COM = GND
1594L/98L F02
DUMMY CONVERSION
CSMUX = CSADC = CS
break-before-make interval, tOPEN. After a delay of tON
(tOFF + tOPEN), the selected channel is switched on,
allowing the ADC in the chip to acquire input signal and
start the conversion (see Figures 1 and 2). After 1 null bit,
the result of the conversion is output on the DOUT line.
The selected channel remains on, until the next falling
edge of CS. At the end of the data exchange, CS should
be brought high. This resets the LTC1594L/LTC1598L
and initiates the next data exchange.
DIN1
DIN2
DOUT1
DOUT2
CS
SHIFT MUX
ADDRESS IN
tSMPL + 1 NULL BIT
SHIFT A/D CONVERSION
RESULT OUT
1594L/98L AI01
Break-Before-Make
The LTC1594L/LTC1598L provide a break-before-make
interval from switching off all the channels simulta-
neously to switching on the next selected channel once
CS is pulled low. In other words, once CS is pulled low,
Data Transfer
The CLK synchronizes the data transfer with each bit
being transmitted on the falling CLK edge and captured
on the rising CLK edge in both transmitting and receiving
systems.
The LTC1594L/LTC1598L first receive input data and
then transmit back the A/D conversion results (half
duplex). Because of the half duplex operation, DIN and
DOUT may be tied together allowing transmission over
just 3 wires: CS, CLK and DATA (DIN/DOUT).
Data transfer is initiated by a rising chip select (CS)
signal. After CS rises, the input data on the DIN pin is
latched into a 4-bit register on the rising edge of the clock.
More than four input bits can be sent to the DIN pin
without problems, but only the last four bits clocked in
before CS falls will be stored into the 4-bit register. This
4-bit input data word will select the channel in the
muliplexer (see Input Data Word and Tables 1 and 2). To
ensure correct operation, the CS must be pulled low
before the next rising edge of the clock.
Once the CS is pulled low, all channels are simulta-
neously switched off after a delay of tOFF to ensure a
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