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參數(shù)資料
| 型號： | LTC1569-7 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Linear Phase, DC Accurate, Tunable, 10th Order Lowpass Filter(線性脈沖，直流精度，可調(diào)諧的10階低通濾波器) |
| 中文描述： | 線性相位，直流準(zhǔn)確，可調(diào)諧，第10階低通濾波器（線性脈沖，直流精度，可調(diào)諧的10階低通濾波器） |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 227K |
| 代理商： | LTC1569-7 |
3
LTC1569-7
Output DC Offset
(Note 2)
R
EXT
= 10k, Pin 5 Shorted to Pin 4
V
S
= 3V
V
S
= 5V
V
S
=
±
5V
V
S
= 3V
V
S
= 5V
V
S
=
±
5V
Min Logical “1”
Max Logical “0”
Min Logical “1”
Max Logical “0”
Min Logical “1”
Max Logical “0”
V
S
= 3V
±
2
±
6
±
15
–25
–25
±
25
2.6
0.5
4.0
0.5
4.0
0.5
6
±
5
±
12
mV
mV
mV
Output DC Offset Drift
R
EXT
= 10k, Pin 5 Shorted to Pin 4
μ
V/
°
C
μ
V/
°
C
μ
V/
°
C
Clock Pin Logic Thresholds
when Clocked Externally
V
S
= 3V
V
V
V
V
V
V
V
S
= 5V
V
S
=
±
5V
Power Supply Current
(Note 3)
f
CLK
= 1.028MHz (10k from Pin 6 to Pin 7,
Pin 5 Open,
÷
4), f
CUTOFF
= 32kHz
8
9
9
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
G
V
S
= 5V
7
G
10
13
14
V
S
= 10V
9
G
f
CLK
= 4.096MHz (10k from Pin 6 to Pin 7,
Pin 5 Shorted to Pin 4,
÷
1), f
CUTOFF
= 128kHz
f
CLK
= 8.192MHz (5k from Pin 6 to Pin 7,
Pin 5 Shorted to Pin 4,
÷
1), f
CUTOFF
= 256kHz
V
S
= 3V
9.5
G
14
V
S
= 5V
20
G
30
V
S
= 10V
27
G
37
4.6
Power Supply Voltage where
Low Power Mode is Enabled
Clock Feedthrough
Wideband Noise
THD
Clock-to-Cutoff
Frequency Ratio
Max Clock Frequency
(Note 4)
Pin 5 Shorted to Pin 4, Note 3
G
3.7
4.2
V
R
EXT
= 10k, Pin 5 Open
Noise BW = DC to 2 f
CUTOFF
f
IN
= 10kHz, 1.5V
P-P
0.4
125
74
32
mV
RMS
μ
V
RMS
dB
V
S
= 3V
V
S
= 5V
V
S
=
±
5V
3V to
±
5V, T
A
< 85
°
C
5
MHz
MHz
MHz
kHz
9.6
13
3
Min Clock Frequency
(Note 5)
Input Frequency Range
Aliased Components <–65dB
0.9 f
CLK
Hz
The
G
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T
A
= 25
°
C.
V
S
= 3V (V
+
= 3V, V
–
= 0V), f
CLK
= 4.096MHz, f
CUTOFF
= 128kHz, R
LOAD
= 10k unless otherwise specified.
ELECTRICAL C
HARA TERISTICS
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Note 1:
Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2:
DC offset is measured with respect to Pin 3.
Note 3:
There are several operating modes which reduce the supply
current. For V
S
< 4V, the current is reduced by 50%. If the internal
oscillator is used as the clock source and the divide-by-4 or divide-by-16
mode is enabled, the supply current is reduced by 60% independent of the
value of V
S
.
Note 4:
The maximum clock frequency is arbitrarily defined as the
frequency at which the filter AC response exhibits >1dB of gain peaking.
Note 5:
The minimum clock frequency is arbitrarily defined as the frequecy
at which the filter DC offset changes by more than 5mV.
Note 6:
Thermal resistance varies depending upon the amount of PC board
metal attached to the device.
θ
JA
is specified for a 2500mm
2
test board
covered with 2oz copper on both sides.
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