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參數(shù)資料
| 型號(hào)： | LTC1564 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 10kHz to 150kHz Digitally Controlled Antialiasing Filter and 4-Bit P.G.A |
| 中文描述： | 10kHz至150kHz的數(shù)字控制抗混疊濾波器和4位美國(guó)PGA |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大小： | 227K |
| 代理商： | LTC1564 |
5
LTC1564
TYPICAL PERFOR U
PIU
OUT (Pin 1):
Analog Output. In normal filtering, this is the
output of an internal operational amplifier and is capable
of swinging essentially to any voltage between the power
supply rails (that is, between V
+
and V
–
). This output is
designed to drive a nominal load of 5k and 50pF. For
lowest signal distortion it should be loaded as lightly as
possible. The output can drive lower resistances than 5k,
but distortion may increase, and the output current will
limit at approximately
±
10mA. Capacitances higher than
50pF should be isolated by a series resistor of 500
to
preserve AC stability. In the Mute state (F code 0000 or
RST = 0), the output operates as in normal filtering but the
gain from the IN pin becomes zero and the output noise is
reduced. In the shutdown state (EN = 1 or EN open
circuited), most of the circuitry in the LTC1564 shuts off
and the OUT pin assumes a high impedance state.
V
–
, V
+
(Pins 2, 14):
Power Supply Pins. The V
+
and V
–
pins should be bypassed with 0.1
μ
F capacitors to an
adequate analog ground plane using the shortest possible
wiring. Electrically clean supplies and a low impedance
ground are important for the high dynamic range and high
stopband suppression available from the LTC1564 (see
further details under AGND). Low noise linear power
supplies are recommended. Switching supplies are not
recommended because of the inevitable risk of their
switching noise coupling into the signal path, reducing
dynamic range.
EN (Pin 3):
CMOS-Level Digital Chip Enable Input. Logic1
or open circuiting this pin causes a shutdown mode with
reduced supply current. The active circuitry in the LTC1564
shuts off and its output assumes a high impedance state.
If F and G bits are latched (CS/HOLD = 1) during the
shutdown state, the latch will retain its contents.
A small pull-up current source at the EN input causes the
LTC1564 to be in shutdown state if the EN pin is left open.
Therefore, the user must connect the EN pin to logic 0 (V
–
or optionally 0V with
±
5V supplies) for normal filter
operation.
CS/HOLD (Pin 4):
CMOS-Level Digital Enable Input for the
Latch Holding F and G Bits. Logic 0 makes the latch
transparent so that the F and G inputs directly control the
filter’s cutoff frequency and gain. Logic 1 holds the last
values of these inputs prior to the transition. This pin floats
to logic 0 (V
–
) when open circuited because of a small
current source (see Electrical Characteristics, Note 5).
F3, F2, F1, F0 (Pins 5, 6, 7, 8):
CMOS-Level Digital
Frequency Control (“F Code”) Inputs. F3 is the most
significant bit (MSB). These pins program the LTC1564’s
cutoff frequency f
C
through the internal latch, which
THD + Noise vs Input Voltage
(f
C
= 100kHz)
INPUT VOLTAGE (V
P-P
)
–80
(
–60
–50
–30
–20
0.001
0.1
1
10
1564 G12
–100
0.01
–40
–70
–90
3V SUPPLY
5V SUPPLY
±
5V SUPPLY
f
C
= 100kHz
f
IN
= 10kHz
BASEBAND GAIN SETTING
2
1
10
100
4
8
1564 G13
I
μ
V
R
)
1
16
f
C
= 100kHz
f
C
= 10kHz
FREQUENCY (Hz)
–60
G
–40
–30
–10
10
0.1k
10k
100k
1M
1564 G14
–80
1k
–20
–50
–70
0
f
C
= 10kHz
V
S
=
±
2.5V
NEGATIVE SUPPLY
V
+
SUPPLY BYPASS = 0.1
μ
F
V
–
SUPPLY BYPASS = NONE
POSITIVE SUPPLY
V
+
SUPPLY BYPASS = NONE
V
–
SUPPLY BYPASS = 0.1
μ
F
Noise vs Frequency
and Gain Settings
Power Supply Rejection
vs Frequency
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