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參數(shù)資料
| 型號： | LTC1519IS#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LINE RCVR RS485 QUAD 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 類型： | 線路接收器 |
| 驅(qū)動器/接收器數(shù)： | 0/4 |
| 規(guī)程： | RS422，RS485 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1354 (CN2011-ZH PDF) |
5
LTC1518/LTC1519
LTC1518
B1 (Pin 1): Receiver 1 Inverting Input.
A1 (Pin 2): Receiver 1 Noninverting Input.
OUT 1 (Pin 3): Receiver 1 Output.
EN (Pin 4): A high enables all outputs; a low on Pin 4 and
a high on Pin 12 will put all outputs into a high impedance
state. Do not float.
OUT 2 (Pin 5): Receiver 2 Output.
A2 (Pin 6): Receiver 2 Noninverting Input.
B2 (Pin 7): Receiver 2 Inverting Input.
GND (Pin 8): Ground Pin. A ground plane is recommended
for all LTC1518 applications.
B3 (Pin 9): Receiver 3 Inverting Input.
A3 (Pin 10): Receiver 3 Noninverting Input.
OUT 3 (Pin 11): Receiver 3 Output.
EN (Pin 12): A low enables all outputs; a low on Pin 4 and
a high on Pin 12 will put all outputs into a high impedance
state. Do not float.
OUT 4 (Pin 13): Receiver 4 Output.
A4 (Pin 14): Receiver 4 Noninverting Input.
B4 (Pin 15): Receiver 4 Inverting Input.
VDD (Pin 16): Power Supply Input. This pin should be
decoupled with a 0.1
F ceramic capacitor as close as
possible to the pin. Recommended: VDD = 5V ±5%.
LTC1519
B1 (Pin 1): Receiver 1 Inverting Input.
A1 (Pin 2): Receiver 1 Noninverting Input.
OUT 1 (Pin 3): Receiver 1 Output.
EN12 (Pin 4): A high enables receivers 1 and 2; a low will
put the outputs of receivers 1 and 2 into a high impedance
state. Do not float.
OUT 2 (Pin 5): Receiver 2 Output.
A2 (Pin 6): Receiver 2 Noninverting Input.
B2 (Pin 7): Receiver 2 Inverting Input.
GND (Pin 8): Ground Pin. A ground plane is recommended
for all LTC1519 applications.
B3 (Pin 9): Receiver 3 Inverting Input.
A3 (Pin 10): Receiver 3 Noninverting Input.
OUT 3 (Pin 11): Receiver 3 Output.
EN34 (Pin 12): A high enables receivers 3 and 4; a low will
put the outputs of receivers 3 and 4 into a high impedance
state. Do not float.
OUT 4 (Pin 13): Receiver 4 Output.
A4 (Pin 14): Receiver 4 Noninverting Input.
B4 (Pin 15): Receiver 4 Inverting Input.
VDD (Pin 16): Power Supply Input. This pin should be
decoupled with a 0.1
F ceramic capacitor as close as
possible to the pin. Recommended: VDD = 5V ±5%.
UU
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PI FU CTIO S
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