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參數(shù)資料
| 型號(hào)： | LTC1450LIG#TR |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 14/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT R-R PAR MPWR 24SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,800 |
| 設(shè)置時(shí)間： | 14µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 750µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
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7
LTC1450/LTC1450L
PIN FUNCTIONS
UU
U
An input code of (000H) will connect the positive input of
the output buffer to this end. Can be used to offset the zero
scale above ground.
REFHI (Pin 18): Upper input terminal of the DAC’s internal
resistor string. Typically connected to REFOUT. An input
code of (FFFH) will connect the positive input of the output
buffer to 1LSB from this end.
REFOUT (Pin 19): Output of the internal 2.048V/1.22V
reference. Typically connected to REFHI to drive internal
DAC resistor string.
VCC (Pin 20): Positive Power Supply Input. 4.5V ≤ VCC ≤
5.5V (LTC1450) and 2.7V
≤ VCC ≤ 5.5V (LTC1450L).
Requires a bypass capacitor to ground.
VOUT (Pin 21): Buffered DAC Output.
X1/X2 (Pin 22): Gain Setting Resistor Pin. Connect to GND
for G = 2 or to VOUT for G = 1. Should always be tied to a
low impedance source, such as ground or VOUT, to ensure
stability of the output buffer when driving capacitive loads.
CLR (Pin 23): Clear Input (Asynchronous Active Low). A
low on this pin asynchronously resets all internal latches
to 0s.
LDAC (Pin 24): Load DAC (Asynchronous Active Low).
Used to asynchronously transfer the contents of the input
latches to the DAC latches which updates the output
voltage. The rising edge latches the data into the DAC
latches. If held low the DAC latches are transparent and
data from the input latches will immediately update VOUT.
WR (Pin 1): Write Input (Active Low). Used with CSMSB
and/or CSLSB to load data into the input latches. While WR
and CSMSB and/or CSLSB are held low the enabled input
latches are transparent. The rising edge of WR will latch
data into all input latches.
CSLSB (Pin 2): Chip Select Least Significant Byte (Active
Low). Used with WR to load data into the eight LSB input
latches. While WR and CSLSB are held low the eight LSB
input latches are transparent. The rising edge will latch
data into the eight LSB input latches. Can be connected to
CSMSB for simultaneous loading of both sets of input
latches on a 12-bit bus.
CSMSB (Pin 3): Chip Select Most Significant Byte (Active
Low). Used with WR to load data into the four MSB input
latches. While WR and CSMSB are held low the four MSB
input latches are transparent. The rising edge will latch
data into the four MSB input latches. Can be connected to
CSLSB for simultaneous loading of both sets of input
latches on a 12-bit bus.
D0 to D7 (Pins 4 to 11): Input data for the Least Significant
Byte. Loaded into LSB input latch when WR = 0 and
CSLSB = 0.
D8, D9, D10, D11 (Pins 12, 13, 14, 15): Input data for the
Most Significant Byte. Loaded into MSB input latch when
WR = 0 and CSMSB = 0. Can be connected to D0 to D3 for
multiplexed operation on an 8-bit bus.
GND (Pin 16): Ground.
REFLO (Pin 17): Lower input terminal of the DAC’s inter-
nal resistor string. Typically connected to Analog Ground.
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