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參數(shù)資料
| 型號(hào)： | LTC1426CS8#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PWM D/A CONV 6BIT DUAL 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 位數(shù)： | 6 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 550µW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | * |
5
LTC1426
BLOCK DIAGRAM
W
APPLICATIONS INFORMATION
WU
U
PWM1
VREF
PWM2
1426 F01
COMPARATOR
DRIVER
6-BIT
UP/DOWN
COUNTER
DEBOUNCE
CIRCUIT
6-BIT
UP
COUNTER
LATCH
AND
LOGIC
CONTROL
LOGIC
MODE SELECT
0 = PUSHBUTTON MODE
1 = PULSE MODE
6-BIT
UP/DOWN
COUNTER
6
POWER-ON
RESET
OSCILLATOR
SHDN
INPUT
CONDITIONING
CLK1
CLK2
Figure 1. LTC1426 Block Diagram
DEFI ITIO S
U
LSB: The least significant bit or the ideal duty cycle
difference between two successive codes.
LSB = DCMAX/64
DCMAX = The DAC output maximum duty cycle
Resolution: The resolution is the number of DAC output
states (64) that divide the full-scale output duty cycle
range. The resolution does not necessarily imply linearity.
INL: End point integral nonlinearity is the maximum devia-
tion from a straight line passing through the end points of
the DAC transfer curve. The INL error at a given code is
calculated as follows:
INL = (DCOUT – DCIDEAL)/LSB
DCIDEAL = (Code)(LSB)
DCOUT = the DAC output duty cycle measured at the
given number of clocked in pulses.
DNL: Differential nonlinearity is the difference between the
measured duty cycle change and the ideal 1LSB duty cycle
change between any two adjacent codes. The DNL error
between any two codes is calculated as follows:
DNL = (
DCOUT – LSB)/LSB
DCOUT = The measured duty cycle difference between
two adjacent codes.
Full-Scale Error: Full-scale error is the difference between
the ideal and measured DAC output duty cycles with all bits
set to one (Code = 63). The full-scale error is calculated as
follows:
FSE = (DCOUT – DCIDEAL)/LSB
DCIDEAL = DCMAX
Dual 6-Bit PWM DAC
Figure 1 shows a block diagram of the LTC1426. Each
6-bit PWM DAC is guaranteed monotonic and is digitally
adjustable in 64 equal steps, which corresponds from 0%
to 98.5% duty cycle full scale. At power-up, the counters
reset to 100000B and both DAC outputs assume midscale
duty cycle. The PWM outputs have an output impedance
of less than 100
. The DAC outputs swing from 0V to the
reference voltage, VREF, which can be biased from 0V to
5.5V. The frequency of the DAC outputs is above 3kHz,
easing output filtering.
In the case of a pure resistive load, the voltage measured
across load RL is given by:
V = (VPWM)RL/(RL + ROUT)
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