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參數(shù)資料
| 型號： | LTC1420CGN#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 10MSPS SAMPL 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 10M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 300mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
13
LTC1420
1420fa
DIGITAL
SYSTEM
1F
3
VCM
–AIN
+AIN
1
2
470pF
1420 F12
1F
5
VREF
6
GND
1F
7
VDD
8
GND
LTC1420
ANALOG GROUND PLANE
1F
23
VDD
1F
22
OVDD
24
GND
1F
25
VSS
21
OGND
+
–
ANALOG
INPUT
CIRCUITRY
Figure 13. Cross Section of LTC1420 Printed Circuit Board
AVOID BREAKING GROUND PLANE
IN THIS AREA
PLACE NON-GROUND
VIAS AWAY FROM
GROUND PLANE AND
BYPASS CAPACITORS
ANALOG
GROUND
PLANE
BYPASS
CAPACITOR
1420 F13
LTC1420
Figure 12. Power Supply Grounding
APPLICATIONS INFORMATION
WU
U
are present. The SNR performance of an ADC when the
performance is limited by jitter is given by:
SNR = – 20log (2π fINtJ)dB
where fIN is the frequency of an input sine wave and tJ is
the root-mean-square jitter due to the clock, the analog
input and the A/D aperture jitter. To minimize clock jitter,
use a clean clock source such as a crystal oscillator, treat
the clock signals as sensitive analog traces and use
dedicated packages with good supply bypassing for any
clock drivers.
Board Layout
To obtain the best performance from the LTC1420, a
printed circuit board with a ground plane is required.
Layout for the printed circuit board should ensure that
digital and analog signal lines are separated as much as
possible. In particular, care should be taken not to run any
digital track alongside an analog signal track.
An analog ground plane separate from the logic system
ground should be placed under and around the ADC.
Pins 6, 8 and 24 (GND), Pin 21 (OGND) and all other
analog grounds should be connected to this ground plane.
In single supply mode, Pin 25 (VSS) should also be
connected to this ground plane. All bypass capacitors for
the LTC1420 should also be connected to this ground
plane (Figure 12). The digital system ground should be
connected to the analog ground plane at only one point,
near the OGND pin.
The analog ground plane should be as close to the ADC as
possible. Care should be taken to avoid making holes in the
analog ground plane under and around the part. To ac-
complish this, we recommend placing vias for power and
signal traces outside the area containing the part and the
decoupling capacitors (Figure 13).
Supply Bypassing
High quality, low series resistance ceramic 1F capacitors
should be used at both VDD pins, VCM and VREF. If VSS is
connected to – 5V it should also be bypassed to ground
with 1F. In single supply operation, VSS should be
shorted to the ground plane as close to the part as
possible. If OVDD is not shorted to Pin 23 (VDD), it also
requires a 1F decoupling capacitor to ground. Surface
mount capacitors such as the AVX 0805ZC105KAT pro-
vide excellent bypassing in a small board space. The traces
connecting the pins and the bypass capacitors must be
kept short and should be made as wide as possible.
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