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參數(shù)資料
| 型號： | LTC1419ISW#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 800KSPS SHDN 28SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 800k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 240mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
16
LTC1419
1419fb
APPLICATIONS INFORMATION
WU
U
DIGITAL INTERFACE
The A/D converter is designed to interface with micropro-
cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a
conversion.
Internal Clock
The A/D converter has an internal clock that eliminates the
need of synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 0.95
s and a maximum conversion time over the
full operating temperature range of 1.15
s. No external
adjustments are required. The guaranteed maximum
acquisition time is 300ns. In addition, a throughput time of
1.25
s and a minimum sampling rate of 800ksps are
guaranteed.
Power Shutdown
The LTC1419 provides two power shutdown modes, nap
and sleep, to save power during inactive periods. The nap
t3
CS
SHDN
1419 F14a
Figure 14a. CS to SHDN Timing
mode reduces the power by 95% and leaves only the
digital logic and reference powered up. The wake-up time
from nap to active is 400ns. In sleep mode, the reference
is shut down and only a small current remains, about
250
A. Wake-up time from sleep mode is much slower
since the reference circuit must power up and settle to
0.005% for full 14-bit accuracy. Sleep mode wake-up
time is dependent on the value of the capacitor connected
to the REFCOMP (Pin 4). The wake-up time is 10ms with
the recommended 10
F capacitor. Shutdown is con-
trolled by Pin 21 (SHDN); the ADC is in shutdown when it
is low. The shutdown mode is selected with Pin 20 (CS);
low selects nap.
Figure 13d. Suggested Evaluation Circuit Board—Solder Side Layout
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