CL DBN (A) Hi-Z TO VOH
參數(shù)資料
型號: LTC1416CG
廠商: Linear Technology
文件頁數(shù): 18/20頁
文件大小: 0K
描述: IC A/D CONV 14BIT SAMPLNG 28SSOP
標(biāo)準(zhǔn)包裝: 47
位數(shù): 14
采樣率(每秒): 400k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 100mW
電壓電源: 雙 ±
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 管件
輸入數(shù)目和類型: 2 個單端,雙極;1 個差分,雙極
7
LTC1416
TEST CIRCUITS
1k
CL
DBN
(A) Hi-Z TO VOH AND VOL TO VOH
(B) Hi-Z TO VOL AND VOH TO VOL
DBN
1k
5V
1416 TC01
Load Circuits for Access Timing
Load Circuits for Output Float Delay
1k
100pF
DBN
(A) VOH TO Hi-Z
(B) VOL TO Hi-Z
DBN
1k
5V
1416 TC02
APPLICATIONS INFORMATION
WU
U
CONVERSION DETAILS
The LTC1416 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion, the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun, it cannot be restarted.
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit
(LSB). Referring to Figure 1, the AIN+ and AIN– inputs are
connected to the sample-and-hold capacitors (CSAMPLE)
during the acquire phase and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum delay of 400ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
During the convert phase the comparator zeroing switches
open, putting the comparator into compare mode. The
input switches connect the CSAMPLE capacitors to ground,
transferring the differential analog input charge onto the
summing junction. This input charge is successively com-
pared with the binary-weighted charges supplied by the
differential capacitive DAC. Bit decisions are made by the
high speed comparator. At the end of a conversion, the
differential DAC output balances the AIN+ and AIN– input
charges. The SAR contents (a 14-bit data word) which
represents the difference of AIN+ and AIN– are loaded into
the 14-bit output latches.
SAMPLE
CSAMPLE
+
CSAMPLE
VDAC
VDAC
+
D13
D0
ZEROING SWITCHES
AIN
+
CDAC
+
CDAC
AIN
14
1416 F01
COMP
+
HOLD
OUTPUT
LATCH
SAR
Figure 1. Simplified Block Diagram
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