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參數(shù)資料
| 型號(hào)： | LTC1415CSW#TR |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 4/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 1.25MSPS SMP 28SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1.25M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 100mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類(lèi)型： | 2 個(gè)單端，雙極；1 個(gè)差分，雙極 |
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12
LTC1415
APPLICATIONS INFORMATION
WU
U
circuitry. The reference amplifier gains the voltage at the
VREF pin by 1.638 to create the required internal reference
voltage of 4.096V. This provides buffering between the
VREF pin and the high speed capacitive DAC. The reference
amplifier compensation pin (REFCOMP, Pin 4) must be
bypassed with a capacitor to ground. The reference ampli-
fier is stable with capacitors of 1
F or greater. For the best
noise performance a 10
F ceramic or tantalum in parallel
with a 0.1
F ceramic is recommended.
R2
40k
R3
64k
REFERENCE
AMP
10
F
REFCOMP
AGND
VREF
R1
2k
BANDGAP
REFERENCE
3
4
5
2.500V
4.096V
LTC1415
LTC1415 F08a
Figure 8a. LTC1415 Reference Circuit
1
2
3
10
F
ANALOG
INPUT
1415 F08b
LT1019A-2.5
VOUT
VIN
5V
+AIN
–AIN
VREF
LTC1415
AGND
REFCOMP
5
4
Figure 8b. Using the LT1019-2.5 as an External Reference
LTC1415
+AIN
DIFFERENTIAL ANALOG INPUT
RANGE = (VREF)(1.638)
–AIN
VREF
REFCOMP
AGND
LTC1415 F09
1
2
3
4
5
10
F
LTC1450
12-BIT
RAIL-TO-RAIL DAC
1.25V TO 3V
Figure 9. Driving VREF with a DAC to Adjust Full Scale
bandwidth and settling time of this circuit. A settling time
of 5ms should be allowed for after a reference adjustment.
Differential Inputs
The LTC1415 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
convert the difference of +AIN – (–AIN) independent of the
common mode voltage. The common mode rejection is
constant from DC to 1MHz, see Figure 10a. The only
requirement is that both inputs can not exceed the AVDD
or AGND power supply voltages. Integral nonlinearity
errors (INL) and differential nonlinearity errors (DNL) are
independent of the common mode voltage, however, the
bipolar zero error (BZE) will vary. The change in BZE is
typically less than 0.1% of the common mode voltage.
Differential inputs allow greater flexibility for accepting
different input ranges. Figure 10b shows a circuit that
shifts the input range up in voltage by 200mV. This can be
useful in applications where the amplifier driving the ADC
input is not able to swing all the way to ground, because
of output loading or settling time issues.
Some AC applications may have their performance limited
by distortion. Most circuits exhibit higher distortion when
signals approach the supply or ground. Distortion can be
reduced by reducing the signal amplitude and keeping the
common mode voltage at approximately midsupply. The
circuit of Figure 10c reduces the ADC full scale from
The VREF pin can be driven with a DAC or other means
shown in Figure 9. This is useful in applications where the
peak input signal amplitude may vary. The input span of
the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio. The filtering
of the internal LTC1415 reference amplifier will limit the
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