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參數(shù)資料
| 型號： | LTC1414IGN#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 14BIT SAMPLNG 28SSOP |
| 標準包裝： | 49 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 2.2M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 230mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
7
LTC1414
APPLICATIONS INFORMATION
WU
U
CONVERSION DETAILS
The LTC1414 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The device is easy to interface with microprocessors and
DSPs. (Please refer to the Digital Interface section for the
data format.)
Conversion start is controlled by the CONVST input. At the
start of the conversion the successive approximation
register (SAR) is reset. Once a conversion cycle has begun
it cannot be restarted.
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit
(LSB). Referring to Figure 1, the AIN+ and AIN– inputs are
connected to the sample-and-hold capacitors (CSAMPLE)
during the acquire phase, and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum delay of 70ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
During the convert phase the comparator zeroing switches
open, putting the comparator into compare mode. The
input switches connect the CSAMPLE capacitors to ground,
transferring the differential analog input charge onto the
summing junction. This input charge is successively com-
pared with the binary-weighted charges supplied by the
differential capacitive DAC. Bit decisions are made by the
high speed comparator. At the end of a conversion, the
differential DAC output balances the AIN+ and AIN– input
charges. The SAR contents (a 14-bit data word) which
represents the difference of AIN+ and AIN– are loaded into
the 14-bit output latches.
DYNAMIC PERFORMANCE
The LTC1414 has excellent high speed sampling capabil-
ity. FFT (Fast Four Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise at
the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 2 shows a
typical LTC1414 FFT plot.
1414 F01
OUTPUT
LATCH
SAR
CDAC
+
CDAC
–
VDAC
–
VDAC
+
–
+
COMP
D13
D0
14
HOLD
AIN
+
AIN
–
ZEROING SWITCHES
CSAMPLE
–
CSAMPLE
+
HOLD
SAMPLE
Figure 1. Simplified Block Diagram
Signal-to-Noise Ratio
The signal-to-(noise + distortion) ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 2a shows a typical spectral content with
a 2.2MHz sampling rate and a 100kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 1.1MHz. (See Figure 2b)
Figure 2a. LTC1414 Nonaveraged, 2048 Point FFT,
Input Frequency = 100kHz
FREQUENCY (kHz)
0
400
800
200
600
1000
AMPLITUDE
(dB)
1414 F02a
0
–20
–40
–60
–80
–100
–120
SINAD = 80dB
SFDR = 96dB
fSAMPLE = 2.2MHz
fIN = 97.753kHz
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