APPLICATIONS INFOR
參數(shù)資料
型號(hào): LTC1412CG#TR
廠商: Linear Technology
文件頁數(shù): 15/16頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 3MSPS SAMPLE 28SSOP
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 12
采樣率(每秒): 3M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 220mW
電壓電源: 雙 ±
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)單端,雙極;1 個(gè)差分,雙極
8
LTC1412
APPLICATIONS INFORMATION
WU
U
COMP
CSAMPLE
+
CDAC
D11
D0
ZEROING SWITCHES
HOLD
AIN
+
AIN
CDAC
+
CSAMPLE
12
1412 F01
+
OUTPUT
LATCHES
VDAC
+
VDAC
HOLD
SAMPLE
HOLD
SAR
Figure 1. Simplified Block Diagram
FREQUENCY (kHz)
0
200
400
600
800 1000 1200 1400
–120
AMPLITUDE
(dB)
–100
–80
–60
–40
0
1412 F02a
–20
fSMPL = 3Msps
fIN = 97.412kHz
SFDR = 93.3dB
SINAD = 73dB
Figure 2a. LTC1412 Nonaveraged, 4096 Point FFT,
Input Frequency = 100kHz
FREQUENCY (kHz)
0
200
400
600
800 1000 1200 1400
–120
AMPLITUDE
(dB)
–100
–80
–60
–40
0
1412 F02B
–20
fSMPL = 3Msps
fIN = 1.419kHz
SFDR = 83dB
SINAD = 72.5dB
SNR = 73db
Figure 2b. LTC1412 Nonaveraged, 4096 Point FFT,
Input Frequency = 1.45MHz
to frequencies from above DC and below half the sampling
frequency. Figure 2 shows a typical spectral content with
a 3MHz sampling rate and a 100kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 1.5MHz.
Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) – 1.76]/6.02
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 3MHz the LTC1412 maintains near ideal ENOBs up
to the Nyquist input frequency of 1.5MHz. Refer to
Figure 3.
sample-and-hold capacitors to acquire the analog signal.
During the convert phase the comparator zeroing switches
open, putting the comparator into compare mode. The
input switches connect the CSAMPLE capacitors to ground,
transferring the differential analog input charge onto the
summing junction. This input charge is successively com-
pared with the binary-weighted charges supplied by the
differential capacitive DAC. Bit decisions are made by the
high speed comparator. At the end of a conversion, the
differential DAC output balances the AIN+ and AIN– input
charges. The SAR contents (a 12-bit data word) which
represents the difference of AIN+ and AIN– are loaded into
the 12-bit output latches.
Dynamic Performance
The LTC1412 has excellent high speed sampling capabil-
ity. FFT (Fast Four Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise at
the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 2 shows a
typical LTC1412 FFT plot.
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
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