t3 NAP/SLP SHDN LTC1409 F14a Figure 14a. NAP/SLP to SHDN T" />
參數(shù)資料
型號: LTC1409ISW#TR
廠商: Linear Technology
文件頁數(shù): 10/20頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 800KSPS SMPL 28SOIC
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 12
采樣率(每秒): 800k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 120mW
電壓電源: 雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,雙極;1 個差分,雙極
18
LTC1409
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
t3
NAP/SLP
SHDN
LTC1409 F14a
Figure 14a. NAP/SLP to SHDN Timing
t2
t1
CS
CONVST
RD
LTC1409 F15
Figure 15. CS to CONVST Setup Timing
t4
SHDN
CONVST
LTC1409 F14b
Figure 14b. SHDN to CONVST Wake-Up Timing
DATA (N – 1)
DB11 TO DB0
CONVST
BUSY
LTC1409 F16
t5
tCONV
t6
t8
t7
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB0
DATA
Figure 16. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
can be latched with the BUSY rising edge. Mode 1a shows
operation with a narrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.
In mode 2 (Figure 18) CS is tied low. The falling edge of
CONVST signal again starts the conversion. Data outputs
are in three-state until read by the MPU with the RD signal.
Mode 2 can be used for operation with a shared MPU
databus.
In slow memory and ROM modes (Figures 19 and 20) CS
is tied low and CONVST and RD are tied together. The MPU
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
In slow memory mode the processor applies a logic low to
RD (= CONVST) starting the conversion. BUSY goes low
forcing the processor into a WAIT state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results ap-
pear on the data outputs; BUSY goes high releasing the
processor, and the processor takes RD (= CONVST) back
high and reads the new conversion data.
In ROM mode, the processor takes RD (= CONVST) low,
starting a conversion and reading the previous conversion
result. After the conversion is complete, the processor can
read the new result and initiate another conversion.
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