The q denotes specifications which apply over the " />
參數(shù)資料
型號: LTC1406IGN#TRPBF
廠商: Linear Technology
文件頁數(shù): 11/16頁
文件大?。?/td> 0K
描述: IC A/D CONV 8BIT SAMPLING 24SSOP
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 8
采樣率(每秒): 20M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 225mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 24-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,雙極;1 個差分,雙極
4
LTC1406
TI I G CHARACTERISTICS
W U
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSMPL(MAX)
Maximum Sampling Frequency
q
20
MHz
t1
Clock Period
(Notes 11, 12)
q
50
ns
t2
Pulse Width High
(Notes 11, 12)
q
25
ns
t3
Pulse Width Low
(Notes 11, 12)
q
25
ns
t4
Output Delay
CL = 15pF
15
25
ns
t5
Pipeline Delay
5
Cycles
t6
Aperture Delay
3ns
Aperture Jitter
5psRMS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, OGND
and AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below ground or above VDD,
they will be clamped by internal diodes. This product can handle input
currents greater than 100mA below ground or above VDD without latchup.
Note 4: When these pin voltages are taken below ground they will be
clamped by internal diodes. This product can handle input currents up to
100mA below ground without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, fSMPL = 20MHz and tr = tf = 2ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended AIN+ input with AIN– tied to VREF = 2.5V.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB
when the output code flickers between 0111 1111 and 1000 0000.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling CLK edge starts a conversion.
Note 12: At the maximum conversion rate, deviation from a 50% duty
cycle results in interstage settling times < 25ns and performance may
be affected.
Note 13: VIN = – Full Scale.
Distortion vs Input Frequency
TYPICAL PERFORMANCE CHARACTERISTICS
UW
INPUT FREQUENCY (Hz)
100k
S/(N
+
D)
(dB)
52
48
44
40
36
32
28
24
20
16
12
8
4
0
1M
10M
100M
1406 G01
S/(N + D) vs Input Frequency
INPUT FREQUENCY (Hz)
100k
AMPLITUDE
(dB
BELOW
THE
FUNDAMENTAL)
0
–10
–20
–30
–40
–50
–60
–70
–80
1M
10M
100M
1406 G03
THD
3RD HARMONIC
2ND HARMONIC
Signal-to-Noise Ratio vs
Input Frequency
INPUT FREQUENCY (Hz)
100k
SIGNAL-TO-NOISE
RATIO
(dB)
52
48
44
40
36
32
28
24
20
16
12
8
4
0
1M
10M
100M
1406 G02
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