APPLICATIONS INFOR
參數(shù)資料
型號(hào)： LTC1404CS8#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 2/24頁(yè)
文件大小： 0K
描述： IC A/D CONV 12BIT W/SHTDN 8-SOIC
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 12
采樣率（每秒）： 600k
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 160mW
電壓電源： 雙 ±
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOIC
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)單端，單極；1 個(gè)單端，雙極
10
LTC1404
1404fa
APPLICATIONS INFORMATION
WU
U
Dynamic Performance
The LTC1404 has excellent high speed sampling capabil-
ity. FFT (Fast Fourier Transform) test techniques are used
to test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 2a shows a
typical LTC1404 FFT plot.
Conversion Details
The LTC1404 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit serial output based on a precision
internal reference. The control logic provides easy inter-
face to microprocessors and DSPs through 3-wire con-
nections.
A rising edge on the CONV input starts a conversion. At the
start of a conversion the successive approximation regis-
ter (SAR) is reset. Once a conversion cycle has begun, it
cannot be restarted.
During conversion, the internal 12-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the AIN input connects to the sample-and-hold
capacitor during the acquired phase and the comparator
offset is nulled by the feedback switch. In this acquire
phase, it typically takes 160ns for the sample-and-hold
capacitor to acquire the analog signal. During the convert
phase, the comparator feedback switch opens, putting the
comparator into the compare mode. The input switches
connect CSAMPLE to ground, injecting the analog input
charge onto the summing junction. This input charge is
successively compared with the binary-weighted charges
supplied by the capacitive DAC. Bit decisions are made by
the high speed comparator. At the end of a conversion, the
DAC output balances the AIN input charge. The SAR
contents (a 12-bit data word) which represent the input
voltage, are presented through the serial pin DOUT.
1404 F01
SAMPLE
DOUT
CDAC
VDAC
DAC
AIN
CSAMPLE
–
+
COMP
S
A
R
SAMPLE
S1
HOLD
Figure 1. AIN Input
FREQUENCY (kHz)
0
60 90 120 150 180 210 240 270 300
AMPLITUDE
(dB)
1404 F02a
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
30
fSAMPLE = 600kHz
fIN = 99.169kHz
SINAD = 72dB
THD = – 88dB
Figure 2a. LTC1404 Nonaveraged, 4096 Point FFT
Plot with 100kHz Input Frequency in Bipolar Mode
Figure 2b. LTC1404 Nonaveraged, 4096 Point FFT
Plot with 300kHz Input Frequency in Bipolar Mode
FREQUENCY (kHz)
0
60 90 120 150 180 210 240 270 300
AMPLITUDE
(dB)
1404 F02b
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
30
fSAMPLE = 600kHz
fIN = 298.681kHz
SINAD = 71dB
THD = – 84dB
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