參數(shù)資料
型號: LTC1403ACMSE-1#TR
廠商: Linear Technology
文件頁數(shù): 8/22頁
文件大?。?/td> 0K
描述: IC ADC 14BIT 2.8MSPS DIFF 10MSOP
標準包裝: 2,500
位數(shù): 14
采樣率(每秒): 2.8M
數(shù)據(jù)接口: 串行,SPI?
轉換器數(shù)目: 1
功率耗散(最大): 12mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)裸露焊盤
供應商設備封裝: 10-MSOP 裸露焊盤
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,單極;1 個差分,單極
配用: DC1082A-D-ND - BOARD SAR ADC LTC1403A
DC1082A-C-ND - BOARD SAR ADC LTC1403A-1
LTC1403-1/LTC1403A-1
16
14031fc
APPLICATIONS INFORMATION
the clock to latch data from the Serial Data Output (SDO)
into your processor serial port. The 14-bit Serial Data
will be received right justified, in a 16-bit word with 16 or
more clocks per frame sync. It is good practice to drive
the LTC1403-1/LTC1403A-1 SCK input first to avoid digi-
tal noise interference during the internal bit comparison
decision by the internal high speed comparator. Unlike the
CONV input, the SCK input is not sensitive to jitter because
the input signal is already sampled and held constant.
Serial Data Output (SDO)
Upon power-up, the SDO output is automatically reset to
the high impedance state. The SDO output remains in high
impedance until a new conversion is started. SDO sends
out 12/14 bits in 2’s complement format in the output data
stream beginning at the third rising edge of SCK after the
rising edge of CONV. SDO is always in high impedance
mode when it is not sending out data bits. Please note
the delay specification from SCK to a valid SDO. SDO is
always guaranteed to be valid by the next rising edge of
SCK. The 16-bit output data stream is compatible with the
16-bit or 32-bit serial port of most processors.
HARDWARE INTERFACE TO TMS320C54x
The LTC1403-1/LTC1403A-1 is a serial output ADC whose
interface has been designed for high speed buffered serial
ports in fast digital signal processors (DSPs). Figure 8
shows an example of this interface using a TMS320C54x.
The buffered serial port in the TMS320C54x has direct
access to a 2kB segment of memory. The ADC’s serial
data can be collected in two alternating 1kB segments,
in real time, at the full 2.8Msps conversion rate of the
LTC1403-1/LTC1403A-1. The DSP assembly code sets
frame sync mode at the BFSR pin to accept an external
positive going pulse and the serial clock at the BCLKR pin
to accept an external positive edge clock. Buffers near
the LTC1403-1/LTC1403A-1 may be added to drive long
tracks to the DSP to prevent corruption of the signal to
LTC1403-1/LTC1403A-1. This configuration is adequate to
traverseatypicalsystemboard,but sourceresistorsatthe
buffer outputs and termination resistors at the DSP, may
be needed to match the characteristic impedance of very
long transmission lines. If you need to terminate the SDO
transmission line, buffer it first with one or two 74ACTxx
gates. The TTL threshold inputs of the DSP port respond
properly to the 3V swing from the SDO pin.
Figure 8. DSP Serial Interface to TMS320C54x
14031 F08
7
10
9
8
6
3-WIRE SERIAL
INTERFACELINK
VDD
CONV
SCK
LTC1403-1/
LTC1403A-1
SDO
VCC
BFSR
BCLKR
TMS320C54x
BDR
GND
CONV
0V TO 3V LOGIC SWING
CLK
3V
5V
B13
B12
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