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參數資料
| 型號： | LTC1402IGN |
| 廠商： | Linear Technology |
| 文件頁數： | 19/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 2.2MSPS SHDN 16SSOP |
| 標準包裝： | 100 |
| 位數： | 12 |
| 采樣率（每秒）： | 2.2M |
| 數據接口： | MICROWIRE?，串行，SPI? |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 150mW |
| 電壓電源： | 模擬和數字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SSOP |
| 包裝： | 管件 |
| 輸入數目和類型： | 2 個單端，單極；2 個單端，雙極；1 個差分，單極；1 個差分，雙極 |
4
LTC1402
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX)
Maximum Sampling Frequency (Conversion Rate)
q
2.2
MHz
tTHROUGHPUT
Minimum Sampling Period (Conversion + Acquisiton Period)
q
455
ns
tSCK
Minimum Clock Period
q
28
10000
ns
tCONV
Conversion Time
(Note 9)
14
SCK cycles
t0
14th SCLK
↑ to CONV↑ Interval
(Notes 9, 10, 16)
q
57
ns
t1
Minimum Positive or Negative SCK Pulse Width
(Note 9)
q
3.8
6
ns
t2
CONV to SCK Setup Time
(Notes 9, 13)
q
7.3
12
ns
t3
SCK After CONV
(Note 9)
q
0ns
t4
Minimum Positive or Negative CONV Pulse Width
(Note 9)
q
3.5
5
ns
t5
SCK to Sample Mode
(Note 9)
q
914
ns
t6
CONV to Hold Mode
(Notes 9, 14)
q
3.4
5
ns
t7
Minimum Delay Between Conversions
(Note 9)
q
48
ns
t8
Minimum Delay from SCK to Valid Bits 0 Through 11
(Notes 9, 15)
q
912
ns
t8a
Minimum Delay from SCK to Valid REFREADY
(Notes 9, 15)
q
15
20
ns
t9
SCK to Hi-Z at DOUT
(Notes 9, 15)
q
11.4
16
ns
t10
Previous DOUT Bit Remains Valid After SCK
(Notes 9, 15)
q
47
ns
t11
REFREADY Bit Delay After Sleep-to-Wake Transition
(Notes 9, 17)
q
10
ms
t12
VREF Settling Time After Sleep-to-Wake Transition
(Notes 9, 17)
q
2ms
The q denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
Positive Supply Voltage
4.75
5.25
V
VSS
Negative Supply Voltage
– 5.25
0
V
IDD
Positive Supply Current
Active Mode
q
18
30
mA
Nap Mode
q
35
mA
Sleep Mode
2
10
A
ISS
Negative Supply Current
Active, Sleep or Nap Modes with SCK Off
q
2
A
PD
Power Dissipation
Active Mode with SCK in Fixed State (Hi or Lo)
90
150
mW
POWER REQUIRE E TS
W
U
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, AGND1
and AGND2 wired together.
Note 3: When these pins are taken below VSS or above VDD, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below VSS or greater than VDD without latchup.
Note 4: When these pins are taken below VSS, they will be clamped by
internal diodes. This product can handle input currents greater than
100mA below VSS or greater than VDD. These pins are not clamped to VDD.
Note 5: VDD = 5V, fSAMPLE = 2.2MHz, VSS = 0V for unipolar mode
specifications and VSS = – 5V for bipolar specifications.
The q denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended AIN
+ input with AIN– grounded and using the internal reference in
bipolar mode with
±5V supplies.
Note 7: Integral linearity is defined as the deviation of a code from the
straight line passing through the actual endpoints of a transfer curve. The
deviation is measured from the center of quantization band.
Note 8: Bipolar offset is the offset measured from – 0.5LSB when the input
flickers between 1000 0000 0000 and 0111 1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The analog input range is defined as the voltage difference
between AIN
+ and AIN–. The bipolar ±2.048V input range could be used
with a single 5V supply if the absolute voltages of the inputs remain within
the single 5V supply voltage.
TI I G CHARACTERISTICS
U
W
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