4.096V or tie to VREF
參數(shù)資料
型號(hào): LTC1402CGN#PBF
廠商: Linear Technology
文件頁(yè)數(shù): 23/24頁(yè)
文件大?。?/td> 0K
描述: IC ADC 12BIT 2.2MSPS SHDN 16SSOP
標(biāo)準(zhǔn)包裝: 100
位數(shù): 12
采樣率(每秒): 2.2M
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 150mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 管件
輸入數(shù)目和類型: 2 個(gè)單端,單極;2 個(gè)單端,雙極;1 個(gè)差分,單極;1 個(gè)差分,雙極
產(chǎn)品目錄頁(yè)面: 1348 (CN2011-ZH PDF)
8
LTC1402
GAIN (Pin 7): Tie to AGND2 to set the reference voltage to
4.096V or tie to VREF to set the reference voltage to 2.048V.
(Note 4)
BIP/UNI (Pin 8): Tie to logic low to set the input range to
unipolar mode or tie to logic high to set the input range to
bipolar mode. (Note 4)
OGND (Pin 9): Output Ground for the Output Driver. This
pin can be tied to the digital ground of the system. All other
ground pins should be tied to the analog ground plane.
DOUT (Pin 10): Three-State Data Output. (Note 3) Each
output data word represents the analog input at the start
of the previous conversion.
OVDD (Pin 11): Output Data Driver Power. Tie to VDD when
driving 5V logic. Tie to 3V when driving 3V logic.
DVDD (Pin 12): Digital Power for Internal Logic. Bypass to
DGND with 10
Fceramic(or10Ftantaluminparallelwith
0.1
F ceramic).
PIN FUNCTIONS
UU
U
DGND (Pin 13): Digital Ground for Internal Logic. Tie to
solid analog ground plane.
VSS (Pin 14): Negative Supply Voltage. Bypass to solid
analog ground plane with 10
F ceramic (or 10F tantalum
in parallel with 0.1
F ceramic) or tie directly to the solid
analog ground plane for single supply use. Must be set
more negative than either AIN+ or AIN – . Set to 0V or – 5V.
SCK (Pin 15): External Clock. Advances the conversion
process and sequences the output data at DOUT on the
rising edge. Responds to 5V or 3V CMOS and to TTL levels.
(Note 4). One or more pulses wake from Nap or Sleep.
CONV (Pin 16): Holds the input analog signal and starts
the conversion on the rising edge. Responds to 5V or 3V
CMOS and to TTL levels. (Note 4). Two pulses with SCK in
fixed high or fixed low state start Nap Mode. Four pulses
with SCK in fixed high or fixed low state start Sleep mode.
BLOCK DIAGRA
W
12-BIT CAPACITIVE DAC
COMP
REF AMP
+
2.048V REF
64k
GAIN
CSAMPLE
CONTROL LOGIC
SCK
CONV
16
15
INTERNAL
CLOCK
OUTPUT
DRIVER
ZEROING SWITCHES
AVDD
1
12
DVDD
14
8
10
11
9
VSS
BIP/UNI
OVDD
DOUT
OGND
AIN
+
3
4
7
5
6
2
13
AIN
AGND1
AGND2
VREF
DGND
1402 BD
+
SUCCESSIVE APPROXIMATION
REGISTER
64k
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